Datasheet

284
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
25.5.2.1 Fixed Priority Arbitration
Fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct priority
pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority pools).
Fixed priority arbitration allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave
by using the fixed priority defined by the user in the MxPR field for each master in the Priority Registers, MATRIX_PRAS
and MATRIX_PRBS. If two or more master requests are active at the same time, the master with the highest priority
MxPR number is serviced first.
In intermediate priority pools, if two or more master requests with the same priority are active at the same time, the
master with the highest number is serviced first.
25.5.2.2 Round-Robin Arbitration
This algorithm is only used in the highest and lowest priority pools. It allows the Bus Matrix arbiters to properly dispatch
requests from different masters to the same slave. If two or more master requests are active at the same time in the
priority pool, they are serviced in a round-robin increasing master number order.
25.6 Write Protect Registers
To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from address
offset 0x000 to 0x1FC can be write-protected by setting the WPEN bit in the MATRIX Write Protect Mode Register
(MATRIX_WPMR).
If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC is detected, then the
WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.
The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR) with the appropriate
access key WPKEY.