Datasheet

280
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
25.2.2 Matrix Slaves
The Bus Matrix manages 9 slaves. Each slave has its own arbiter, thus allowing a different arbitration per slave to be
programmed.
25.2.3 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access
from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired,
and shown as “-” in the following table.
Table 25-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1 Internal ROM
Slave 2 Soft Modem (SMD)
Slave 3
USB Device High Speed Dual Port RAM (DPR)
USB Host EHCI registers
USB Host OHCI registers
Slave 4 External Bus Interface
Slave 5 DDR2 port 1
Slave 6 DDR2 port 2
Slave 7 DDR2 port 3
Slave 8 Peripheral Bridge 0
Slave 9 Peripheral Bridge 1
Table 25-3. Master to Slave Access
Masters 0 1 2&3 4&5 6 7 8 9 10 11
Slaves
ARM926
Instr.
ARM926
Data DMA 0 DMA 1
USB
Device HS
DMA
USB Host
HS EHCI
USB Host
HS OHCI LCD DMA Reserved Reserved
0 Internal SRAM X X X X X X X X X X
1 Internal ROM X X X X - - - - - -
2SMD XX-X- -- - - -
3
USB Device High
Speed DPR
USB Host EHCI
registers
USB Host OHCI
registers
XX--- -- - - -
4 External Bus Interface X X X X X X X X X X
5 DDR2 Port 1 X - X - - -- - - -
6 DDR2 Port 2 - X - X - -- - - -
7 DDR2 Port 3 - - - - - -- X - -
8 Peripheral Bridge 0 X X X X - - - - - -
9 Peripheral Bridge 1 X X X X - - - - - -