Datasheet
279
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
25. Bus Matrix (MATRIX)
25.1 Description
The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths
between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix
interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one
cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus and provides a Chip Configuration User
Interface with Registers that allow the Bus Matrix to support application specific features.
25.2 Embedded Characteristics
z 12-layer Matrix, handling requests from 11 masters
z Programmable Arbitration strategy
z Fixed-priority Arbitration
z Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
z Burst Management
z Breaking with Slot Cycle Limit Support
z Undefined Burst Length Support
z One Address Decoder provided per Master
z Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one for
internal flash boot, one after remap
z Boot Mode Select
z Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0
z Selection is made by General purpose NVM bit sampled at reset
z Remap Command
z Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash)
z Allows Handling of Dynamic Exception Vectors
25.2.1 Matrix Masters
The Bus Matrix manages 12 masters, which means that each master can perform an access concurrently with others,
depending on whether the slave it accesses is available.
Each master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing,
all the masters have the same decodings.
Table 25-1. List of Bus Matrix Masters
Master 0 ARM926 Instruction
Master 1 ARM926 Data
Master 2&3 DMA Controller 0
Master 4&5 DMA Controller 1
Master 6 UDP HS DMA
Master 7 UHP EHCI DMA
Master 8 UHP OHCI DMA
Master 9 LCD DMA
Master 10 Reserved