Datasheet

263
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
z ARCH - identifies the set of embedded peripherals
z SRAMSIZ - indicates the size of the embedded SRAM
z EPROC - indicates the embedded ARM processor
z VERSION - gives the revision of the silicon
The second register is device-dependent and reads 0 if the bit EXT is 0.
24.5.8 ICE Access Prevention
The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is
implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface.
Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller.
On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access.
This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.