Datasheet

175
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
22. Power Management Controller (PMC)
22.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral
clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core.
22.2 Embedded Characteristics
The Power Management Controller provides all the clock signals to the system.
PMC input clocks:
z UPLLCK : From UTMI PLL
z PLLACK : From PLLA
z SLCK: slow clock from external 32 kHz oscillator or internal 32 kHz RC oscillator
z MAINCK: Main Clock from external 12 MHz oscillator or internal 12 MHz RC Oscillator
PMC output clocks:
z Processor Clock PCK.
z Master Clock MCK, in particular to the Matrix, the memory interfaces, the peripheral bridge. The divider can be 2,
3 or 4.
z Each peripheral embeds its own divider, programmable in the PMC User Interface.
z 133 MHz DDR clock
Note: DDR clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
z LCD pixel clock that can use DDR clock or MCK, the choice is done in the LCD user interface.
z USB Host EHCI High speed clock (UPLLCK)
z USB OHCI clocks (UHP48M and UHP12M)
z Two programmable clock outputs: PCK0 and PCK1
z SMD clock
This allows software control of five flexible operating modes:
z Normal Mode, processor and peripherals running at a programmable frequency
z Idle Mode, processor stopped waiting for an interrupt
z Slow Clock Mode, processor and peripherals running at low frequency
z Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for
an interrupt
z Backup Mode, Main Power Supplies off, VDDBU powered by a battery