Datasheet

1153
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
48. SAM9G15 Errata
48.1 External Bus Interface (EBI)
48.1.1 EBI: Data lines are Hi-Z after reset
Data lines are Hi-Z after reset. This does not affect boot capabilities neither on NOR nor on NAND memories.
Problem Fix/Workaround
None.
48.2 Reset Controller (RSTC)
48.2.1 RSTC: Reset during SDRAM Accesses
When a Reset (user reset, watchdog, software reset) occurs during SDRAM read access, the SDRAM clock is turned off
while data is ready to be read on the data bus. The SDRAM maintains the data until the clock restarts.
This leads to a data bus conflict and affects adversely the boot memories connected on the EBI:
z NAND Flash boot functionality, if the system boots out of the internal ROM.
z NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
Problem Fix/Workaround
1. Boot from Serial Flash or Data Flash on SPI
2. Connect the NAND Flash on D16-D23 and set NFD0_ON_D16 to 1 in the CCFG_EBICSA register.
Warning! This prohibits to connect another device on the EBI.
3.
48.3 Static Memory Controller (SMC)
48.3.1 SMC: SMC DELAY I/O Registers are write-only
Contrary to what is stated in the datasheet, the SMC DELAY I/O Registers are Write-only.
Problem Fix/Workaround
None.