Datasheet

1146
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or
5 or 7 (Receive Start Selection), two Periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the
TK (or RK) edge and the signal change. The Max access time is the time between the TK edge and the signal stabili-
zation. Figure 45-20 illustrates Min and Max accesses for SSC0. The same applies to SSC1, SSC4, and SSC7,
SSC10 and SSC13.
3. 1.8V domain: V
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 20pF.
4. 3.3V domain: V
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 30pF.
Figure 45-20.Min and Max access time of output signals
45.17.3 HSMCI
The High Speed MultiMedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD
Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
45.17.4 USART in SPI Mode Timings
45.17.4.1Timing conditions
Timings are given assuming a capacitance load on
Table 45-38.
TK (CKI =0)
TF/TD
SSC
0min
TK (CKI =1)
SSC
0max
Table 45-40. Capacitance Load
Corner
Supply MAX MIN
3.3V 40pF 5 pF
1.8V 20pF 5 pF