Datasheet

1008
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
44.7.10 LCD Controller Status Register
Name: LCDC_LCDSR
Address: 0xF8038028
Access: Read-only
Reset: 0x00000000
• CLKSTS: Clock Status
0: Pixel Clock is disabled.
1: Pixel Clock is running.
• LCDSTS: LCD Controller Synchronization status
0: Timing Engine is disabled.
1: Timing Engine is running.
• DISPSTS: LCD Controller DISP Signal Status
0: DISP is disabled.
1: DISP signal is activated.
• PWMSTS: LCD Controller PWM Signal Status
0: PWM is disabled.
1: PWM signal is activated.
• SIPSTS: Synchronization In Progress
0: Clock domain synchronization is terminated.
1: A double domain synchronization is in progress, access to the LCDC_LCDEN and LCDC_LCDDIS registers has no effect.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – SIPSTS PWMSTS DISPSTS LCDSTS CLKSTS