Datasheet

1004
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
• MODE: LCD Controller Output Mode
• VSPSU: LCD Controller Vertical Synchronization Pulse Setup Configuration
0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge.
1: The vertical synchronization pulse is asserted one pixel clock cycle before the horizontal pulse.
• VSPHO: LCD Controller Vertical Synchronization Pulse Hold Configuration
0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge.
1: The vertical synchronization pulse is held active one pixel clock cycle after the horizontal pulse.
• GUARDTIME: LCD DISPLAY Guard Time
Number of frames inserted during start up before LCD_DISP assertion.
Number of frames inserted after LCD_DISP reset.
Table 44-56.
Value Name Description
0 OUTPUT_12BPP LCD output mode is set to 12 bits per pixel
1 OUTPUT_16BPP LCD output mode is set to 16 bits per pixel
2 OUTPUT_18BPP LCD output mode is set to 18 bits per pixel
3 OUTPUT_24BPP LCD output mode is set to 24 bits per pixel