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11052D–ATARM–31-Oct-12

Features

• Core

– ARM926EJ-S™ ARM

Thumb

Processor running at up to 400 MHz @ 1.0V +/- 10%

– 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit

• Memories

– One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash,

SDCard, DataFlash

or serial DataFlash. Programmable order.

– One 32-Kbyte internal SRAM, single-cycle access at system speed

– High Bandwidth Multi-port DDR2 Controller

– 32-bit External Bus Interface supporting 4-bank and 8-bank DDR2/LPDDR,

SDR/LPSDR, Static Memories

– MLC/SLC 8-bit NAND Controller, with up to 24-bit Programmable Multi-bit Error

Correcting Code (PMECC)

• System running at up to 133 MHz

– Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval Timer,

Watchdog Timer and Real Time Clock

– Boot Mode Select Option, Remap Command

– Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators

– Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator

– One PLL for the system and one PLL at 480 MHz optimized for USB High Speed

– Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers

– Dual Peripheral Bridge with dedicated programmable clock for best performances

– Two dual port 8-channel DMA Controllers

– Advanced Interrupt Controller and Debug Unit

– Two Programmable External Clock Signals

• Low Power Mode

– Shut Down Controller with four 32-bit Battery Backup Registers

– Clock Generator and Power Management Controller

– Very Slow Clock Operating Mode, Software Programmable Power Optimization

Capabilities

• Peripherals

– LCD Controller with overlay, alpha-blending, rotation, scaling and color conversion

– USB Device High Speed, USB Host High Speed and USB Host Full Speed with

dedicated On-Chip Transceiver

– Two High Speed Memory Card Hosts

– Two Master/Slave Serial Peripheral Interfaces

– Two Three-channel 32-bit Timer/Counters

– One Synchronous Serial Controller

– One Four-channel 16-bit PWM Controller

– Three Two-wire Interfaces

– Three USARTs, two UARTs

11052D–ATARM–31-Oct-12

AT91SAM ARM-based Embbedded MPU

SAM9G15

DATASHEET

Summary of content (1172 pages)

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AT91SAM ARM-based Embbedded MPU SAM9G15 DATASHEET Features • Core • • • • – ARM926EJ-S™ ARM® Thumb® Processor running at up to 400 MHz @ 1.0V +/- 10% – 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit Memories – One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, SDCard, DataFlash® or serial DataFlash. Programmable order.
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– – – • I/O – – – – One 12-channel 10-bit Touch-Screen Analog-to-Digital Converter Soft Modem Write Protected Registers Four 32-bit Parallel Input/Output Controllers 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output • Package • 217-ball BGA, pitch 0.
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1. Description The SAM9G15, based on the ARM926EJ-S processor, runs at 400 MHz and integrates a rich set of peripherals to support embedded industrial applications that require advanced user interfaces and high-speed communication. The SAM9G15 features a graphics LCD controller with 4-layer overlay and 2D acceleration (picture-in-picture, alphablending, scaling, rotation, color conversion), and a 10-bit ADC that supports 4/5-wire resistive touchscreen panels.
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Block Diagram PC T TS 1 CK -P K0 FIQ IRQ XD DR D X DT N XI UT XO DC DBGU AIC System Controller OSC12M RSTC RTC RC 4 GPBR WDT PIT PLLA PLLUTMI PMC 12M RC OSC 32K SHDC POR PIOC PIOD POR PIOB PIOA MMU D DCache 16 KB I Bus Interface ROM 32 KB + 96 KB ICache 16 KB ARM926EJ-S In-Circuit Emulator JTAG / Boundary Scan JT AG S Peripheral Bridge SSC FS Transc. HS Transc.
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3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1.
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Table 3-1.
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Table 3-1.
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Table 3-1.
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4. Package and Pinout The SAM9G15 is available in a 217-ball BGA package. 4.1 Overview of the 217-ball BGA Package Figure 4-1 shows the orientation of the 217-ball BGA Package. Figure 4-1.
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4.2 I/O Description Table 4-1. SAM9G15 I/O Type Description I/O Type Voltage Range GPIO Analog Pull-up Pull-down Schmitt Trigger 1.65-3.6V switchable switchable switchable GPIO_CLK 1.65-3.6V switchable switchable switchable GPIO_CLK2 1.65-3.6V switchable switchable switchable GPIO_ANA 3.0-3.6V EBI 1.65-1.95V, 3.03.6V switchable switchable EBI_O 1.65-1.95V, 3.03.6V Reset State Reset State EBI_CLK 1.65-1.95V, 3.03.6V I switchable switchable RSTJTAG 3.0-3.
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Table 4-2. 4.2.1 SAM9G15 I/O Type Assignment and Frequency (Continued) I/O Type I/O Frequency (MHz) Charge Load (pF) Output Current USBHS 480 10 HHSDPA, HHSDPB/DHSDP, HHSDMA, HHSDMB/DHSDM CLOCK 50 50 XIN, XOUT, XIN32, XOUT32 DIB 25 25 DIBN, DIBP Signal Name Reset State In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics. z “PIO” “/” signal Indicates whether the PIO Line resets in I/O mode or in peripheral mode.
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4.3 217-ball BGA Package Pinout Table 4-3.
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Table 4-3.
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Table 4-3.
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Table 4-3.
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Table 4-3.
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Table 4-3.
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5. Power Considerations 5.1 Power Supplies The SAM9G15 has several types of power supply pins. Table 5-1. SAM9G15 Power Supplies Name Voltage Range, nominal Powers VDDCORE 0.9-1.1V, 1.0V ARM core, internal memories, internal peripherals and part of the system controller. GNDCORE External Memory Interface I/O lines GNDIOM 3.0-3.6V, 3.3V NAND Flash I/O and control, D16-D32 and multiplexed SMC lines GNDIOM VDDIOP0 1.65-3.6V a part of Peripheral I/O lines(1) GNDIOP VDDIOP1 1.65-3.
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6. Memories Figure 6-1.
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6.1 Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. Banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects, EBI_NCS0 to EBI_NCS5.
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6.3.
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7. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories.
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Figure 7-1. SAM9G15 System Controller Block Diagram System Controller VDDCORE Powered irq fiq periph_irq[2..
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7.1 7.2 Chip Identification z Chip ID: 0x819A_05A1 z Chip ID Extension: 0 z JTAG ID: 0x05B2_F03F z ARM926 TAP ID: 0x0792_603F Backup Section The SAM9G15 features a Backup Section that embeds: z RC Oscillator z Slow Clock Oscillator z Real Time Counter (RTC) z Shutdown Controller z 4 Backup Registers z Slow Clock Control Register (SCKCR) z Boot Sequence Configuration Register (BSCR) z A part of the reset Controller (RSTC) This section is powered by the VDDBU rail.
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8. Peripherals 8.1 Peripheral Mapping As shown in Figure 6-1, the Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xF000 0000 and 0xFFFF C000. Each User Peripheral is allocated 16 Kbytes of address space. 8.2 Peripheral Identifiers Table 8-1 defines the Peripheral Identifiers of the SAM9G15.
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Table 8-1. 8.3 Peripheral Identifiers (Continued) Instance ID Instance Name Instance Description 25 LCDC 26 HSMCI1 High Speed Multimedia Card Interface 1 28 SSC Synchronous Serial Controller 31 AIC Advanced Interrupt Controller External interrupt Wired-OR interrupt LCD Controller IRQ Peripheral Signal Multiplexing on I/O Lines The SAM9G15 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set.
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9. ARM926EJ-S™ 9.1 Description The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density.
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z z z z z 4-address Address Buffer z Software Control Drain DCache Write-back Buffer z 8 Data Word Entries z One Address Entry z Software Control Drain Memory Management Unit (MMU) z Access Permission for Sections z Access Permission for Large Pages and Small Pages z 16 Embedded Domains z 64 Entry Instruction TLB and 64 Entry Data TLB Memory Access z 8-, 16-, and 32-bit Data Types z Separate AMBA AHB Buses for Both the 32-bit Data Interface and the 32-bit Instructions Interface Bus
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9.3 Block Diagram Figure 9-1.
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9.4 ARM9EJ-S Processor 9.4.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: z ARM state: 32-bit, word-aligned ARM instructions. z THUMB state: 16-bit, halfword-aligned Thumb instructions. z Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 9.4.
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9.4.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: z User mode is the usual ARM program execution state. It is used for executing most application programs z Fast Interrupt (FIQ) mode is used for handling fast interrupts.
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Table 9-1. ARM9TDMI Modes and Registers Layout (Continued) User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode SPSR_ABO RT SPSR_UNDEF SPSR_IRQ SPSR_SVC Fast Interrupt Mode SPSR_FIQ Mode-specific banked registers The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values.
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Figure 9-2.
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When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: z ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception).
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Table 9-2.
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Table 9-3. Mnemonic QDADD QSUB QDSUB Notes: 1. New ARM Instruction Mnemonic List (Continued) Mnemonic Operation Saturated Add with Double Operation LDRD Load Double Saturated subtract LDC2 Alternative Load to Coprocessor Saturated Subtract with double CLZ Count Leading Zeroes A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. 9.4.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set.
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z z MMU Other system options To control these features, CP15 provides 16 additional registers. See Table 9-5. Table 9-5.
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9.5.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: z MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. z MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
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9.6 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS, WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13.
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The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Page-mapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A sectionmapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch.
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9.7.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. 9.7.2.1 DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface.
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9.8 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: 9.8.
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10. 10.1 Debug and Test Description The SAM9G15 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel.
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Block Diagram Figure 10-1. Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP Boundary Port JTAGSEL TDO RTCK POR Reset and Test ARM9EJ-S TST ICE-RT ARM926EJ-S DMA DBGU PIO 10.
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10.4 Application Examples 10.4.1 Debug Environment Figure 10-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 10-2.
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10.4.2 Test Environment Figure 10-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 10-3.
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10.5 Debug and Test Pin Description Table 10-1.
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10.6 Functional Description 10.6.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 10.6.2 EmbeddedICE™ The ARM9EJ-S Embedded ICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface.
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A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The device Debug Unit Chip ID value is 0x819A_05A0 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 10.6.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high.
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10.6.6 JTAG ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B2F • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_F03F.
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11. Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed thanks to the BMS pin. This allows the user to layout the ROM or an external memory to 0x0. The sampling of the BMS pin is done at reset. If BMS is detected at 0, the controller boots on the memory connected to Chip Select 0 of the External Bus Interface.
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Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode. 2. Main Oscillator Detection: the Main Clock is switched to the 32 kHz RC oscillator to allow external clock frequency to be measured. Then the Main Oscillator is enabled and set in bypass mode. If the MOSCSELS bit rises, an external clock is connected, and the next step is Main Clock Selection (3). If not, the bypass mode is cleared to attempt external quartz detection.
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Figure 11-2.
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11.4.2 NVM Bootloader Program Description Figure 11-3. NVM Bootloader Program Diagram Start Initialize NVM Initialization OK ? No Restore the reset values for the peripherals and Jump to next boot solution Yes Valid code detection in NVM NVM contains valid code No Yes Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals.
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Figure 11-4. Remap Action after Download Completion 0x0000_0000 0x0000_0000 REMAP Internal ROM Internal SRAM 0x0010_0000 0x0010_0000 Internal ROM Internal ROM 0x0030_0000 0x0030_0000 Internal SRAM Internal SRAM 11.4.3 Valid Code Detection There are two kinds of valid code detection. 11.4.3.1 ARM Exception Vectors Check The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven ARM exception vectors.
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Figure 11-7. Structure of the ARM Vector 6 31 0 Size of the code to download in bytes The value has to be smaller than 24 kbytes. This size is the internal SRAM size minus the stack size used by the ROM Code at the end of the internal SRAM. Example An example of valid vectors follows: 00 ea000006 04 eafffffe 08 ea00002f 0c eafffffe 10 eafffffe 14 00001234 18 eafffffe B0x20 B0x04 B_main B0x0c B0x10 B0x14<- Code size = 4660 bytes B0x18 11.4.3.2 boot.
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Figure 11-8. Boot NAND Flash Download Start Initialize NAND Flash interface Send Reset command No First page contains valid header Yes No NAND Flash is ONFI Compliant Yes Read NAND Flash and PMECC parameters from the header Read NAND Flash and PMECC parameters from the ONFI Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals.
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NAND Flash Specific Header Detection This is the first method used to determine NAND Flash parameters. After Initialization and Reset command, the Boot Program reads the first page without ECC check, to determine if the NAND parameter header is present. The header is made of 52 times the same 32-bit word (for redundancy reasons) which must contain NAND and PMECC parameters used to correctly perform the read of the rest of the data in the NAND.
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11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction NAND Flash boot procedure uses PMECC to detect and correct errors during NAND Flash read operations in two cases: z When the usePmecc flag is set in the specific NAND header. If the flag is not set, no ECC correction is performed during NAND Flash page read. z When the NAND Flash has been detected using ONFI parameters.
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The Galois field tables are mapped in the ROM just after the ROM code, as described in Figure 11-9 below: Figure 11-9. Galois Field Table Mapping 0x0010_0000 ROM Code 0x0010_8000 0x0011_0000 Galois field tables for 512-byte sectors correction Galois field tables for 1024-byte sectors correction For a full description and an example of how to use the PMECC detection and correction feature, refer to the software package dedicated to this device on Atmel’s web site. 11.4.4.
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Table 11-3. DataFlash Device (Continued) Device Density Page Size (bytes) Number of Pages AT45DB161 16 Mbits 528 4096 AT45DB321 32 Mbits 528 8192 AT45DB642 64 Mbits 1056 8192 Supported Serial Flash Devices The SPI Flash Boot program supports all SPI Serial Flash devices responding correctly at both Get Status and Continuous Read commands. 11.4.4.5 TWI EEPROM Boot The TWI EEPROM Bootloader uses the TWI0. It uses only one valid code detection. It analyzes the ARM exception vectors.
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Table 11-4.
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11.5 SAM-BA Monitor If no valid code has been found in NVM during the NVM bootloader sequence, the SAM-BA Monitor program is launched. The SAM-BA Monitor principle is to: z Initialize DBGU and USB z Check if USB Device enumeration has occurred z Check if characters have been received on the DBGU Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in Table 11-5. Figure 11-10.
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z z z Note: z z z z Normal mode configures SAM-BA Monitor to send / receive data in binary format, z Terminal mode configures SAM-BA Monitor to send / receive data in ascii format. Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. z Address: Address in hexadecimal. z Value: Byte, halfword or word to write in hexadecimal. z Output: ‘>’ Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. z Address: Address in hexadecimal.
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Figure 11-11.Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 11.5.3 USB Device Port 11.5.3.1 Supported External Crystal / External Clocks The only frequency supported by SAM-BA Monitor to allow USB communication is a 12 MHz crystal or external clock. 11.5.3.2 USB Class The device uses the USB Communication Device Class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB.
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The device also handles some class requests defined in the CDC class. Table 11-7. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 11.5.3.
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12. Boot Sequence Controller (BSC) 12.1 Description The System Controller embeds a Boot Sequence Configuration Register to save timeout delays on boot. The boot sequence is programmable through the Boot Sequence Configuration Register (BSC_CR). This register is powered by VDDBU, the modification is saved and applied after the next reset. The register is taking Factory Value in case of battery removing. This register is programmable with user programs or SAM-BA and it is key-protected. 12.
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12.4 Boot Sequence Controller (BSC) User Interface Table 12-1. Register Mapping Offset 0x0 Register Name Boot Sequence Configuration Register BSC_CR Access Reset Read-write – 12.4.
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13. Advanced Interrupt Controller (AIC) 13.1 Description The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
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13.
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13.3 Block Diagram Figure 13-1. Block Diagram FIQ AIC ARM Processor IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded nFIQ nIRQ Peripheral Embedded Peripheral APB 13.4 Application Block Diagram Figure 13-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 13.
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13.6 I/O Line Description Table 13-1. I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0 - IRQn Interrupt 0 - Interrupt n Input 13.7 Product Dependencies 13.7.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function.
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13.8 Functional Description 13.8.1 Interrupt Source Control 13.8.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode.
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Figure 13-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Edge Fast Interrupt Controller or Priority Controller AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR Figure 13-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg. Edge Detector Set FF Clear AIC_ISCR AIC_IDCR AIC_ICCR 13.8.
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Figure 13-6. External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles Figure 13-7. External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles Figure 13-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.
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Figure 13-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 13.8.3 Normal Interrupt 13.8.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing).
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This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler.
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7. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack.
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When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR.
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Figure 13-10.Fast Forcing Source 0 _ FIQ AIC_IPR Input Stage Automatic Clear AIC_IMR nFIQ Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR Source n AIC_IPR Input Stage Priority Manager Automatic Clear nIRQ AIC_IMR Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. 13.8.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations.
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13.8.6 Spurious Interrupt The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: z An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time.
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13.10 Advanced Interrupt Controller (AIC) User Interface 13.10.1 Base Address The AIC is mapped at the address 0xFFFFF000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset. Table 13-3.
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13.10.2 AIC Source Mode Register Name: AIC_SMR0..
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13.10.3 AIC Source Vector Register Name: AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.
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13.10.4 AIC Interrupt Vector Register Name: AIC_IVR Address: 0xFFFFF100 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV • IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt.
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13.10.5 AIC FIQ Vector Register Name: AIC_FVR Address: 0xFFFFF104 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
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13.10.6 AIC Interrupt Status Register Name: AIC_ISR Address: 0xFFFFF108 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – IRQID • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number.
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13.10.
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13.10.
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13.10.9 AIC Core Interrupt Status Register Name: AIC_CISR Address: 0xFFFFF114 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ • NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active.
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13.10.10AIC Interrupt Enable Command Register Name: AIC_IECR Address: 0xFFFFF120 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Enable 0 = No effect.
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13.10.11AIC Interrupt Disable Command Register Name: AIC_IDCR Address: 0xFFFFF124 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect.
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13.10.12AIC Interrupt Clear Command Register Name: AIC_ICCR Address: 0xFFFFF128 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Clear 0 = No effect.
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13.10.13AIC Interrupt Set Command Register Name: AIC_ISCR Address: 0xFFFFF12C Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect.
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13.10.14AIC End of Interrupt Command Register Name: AIC_EOICR Address: 0xFFFFF130 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – – The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
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13.10.15AIC Spurious Interrupt Vector Register Name: AIC_SPU Address: 0xFFFFF134 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register.
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13.10.16AIC Debug Control Register Name: AIC_DCR Address: 0xFFFFF138 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – GMSK PROT This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register • PROT: Protection Mode 0 = The Protection Mode is disabled.
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13.10.17AIC Fast Forcing Enable Register Name: AIC_FFER Address: 0xFFFFF140 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Enable 0 = No effect.
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13.10.18AIC Fast Forcing Disable Register Name: AIC_FFDR Address: 0xFFFFF144 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Disable 0 = No effect.
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13.10.20AIC Write Protect Mode Register Name: AIC_WPMR Address: 0xFFFFF1E4 Access: Read-write Reset: See Table 13-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII).
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13.10.21AIC Write Protect Status Register Name: AIC_WPSR Address: 0xFFFFF1E8 Access: Read-only Reset: See Table 13-3 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the AIC_WPSR register.
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14. Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.
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14.3 Block Diagram Figure 14-1.
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14.4 Functional Description 14.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: z proc_nreset: Processor reset line. It also resets the Watchdog Timer. z backup_nreset: Affects all the peripherals powered by VDDBU. z periph_nreset: Affects the whole set of embedded peripherals. z nrst_out: Drives the NRST pin.
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14.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
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Figure 14-4. General Reset State SLCK Any Freq.
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14.4.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset.
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Figure 14-6. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Processor Startup proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 14.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: z PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
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Figure 14-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 to 2 cycles Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 14.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.
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Figure 14-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 14.4.
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14.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: z RSTTYP field: This field gives the type of the last reset, as explained in previous sections. z SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
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14.5 Reset Controller (RSTC) User Interface Table 14-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 Note: Access Reset Back-up Reset RSTC_CR Write-only - Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 Mode Register RSTC_MR Read-write - 0x0000_0000 The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
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14.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFE00 Access Type: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect.
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14.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFE04 Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
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14.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFE08 Access Type: Read-write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 – KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 – 3 – ERSTL 2 – • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds.
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15. Real-time Clock (RTC) 15.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.
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15.3 Block Diagram Figure 15-1.
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15.4 Product Dependencies 15.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 15.4.2 Interrupt Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts. Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first.
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15.5.4 Error Checking when Programming Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag.
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Figure 15-2.
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15.6 Real-time Clock (RTC) User Interface Table 15-1.
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15.6.1 RTC Control Register Name: RTC_CR Address: 0xFFFFFEB0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters.
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15.6.2 RTC Mode Register Name: RTC_MR Address: 0xFFFFFEB4 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected.
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15.6.3 RTC Time Register Name: RTC_TIMR Address: 0xFFFFFEB8 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units.
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15.6.4 RTC Calendar Register Name: RTC_CALR Address: 0xFFFFFEBC Access: Read-write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units.
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15.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0xFFFFFEC0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled.
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15.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0xFFFFFEC4 Access: Read-write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled.
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15.6.7 RTC Status Register Name: RTC_SR Address: 0xFFFFFEC8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 (FREERUN) = Time and calendar registers cannot be updated. 1 (UPDATE) = Time and calendar registers can be updated.
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15.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0xFFFFFECC Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0 = No effect.
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15.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0xFFFFFED0 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect.
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15.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0xFFFFFED4 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect.
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15.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0xFFFFFED8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled.
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15.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0xFFFFFEDC Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed.
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16. Periodic Interval Timer (PIT) 16.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.
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16.3 Block Diagram Figure 16-1.
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16.4 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
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16.5 Periodic Interval Timer (PIT) User Interface Table 16-1.
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16.5.1 Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFE30 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 14 13 12 25 PITIEN 24 PITEN 17 16 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
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16.5.2 Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFE34 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
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16.5.3 Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFE38 Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.
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16.5.4 Periodic Interval Timer Image Register Name: PIT_PIIR Address: 0xFFFFFE3C Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
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17. Watchdog Timer (WDT) 17.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 17.
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17.3 Block Diagram Figure 17-1.
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17.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
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Figure 17-2.
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17.5 Watchdog Timer (WDT) User Interface Table 17-1.
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17.5.1 Watchdog Timer Control Register Register Name: WDT_CR Address: 0xFFFFFE40 Access Type: 31 Write-only 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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17.5.2 Watchdog Timer Mode Register Register Name: WDT_MR Address: 0xFFFFFE44 Access Type: Read-write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 18 11 10 22 26 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
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17.5.3 Watchdog Timer Status Register Register Name: WDT_SR Address: 0xFFFFFE48 Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
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18. Shutdown Controller (SHDWC) 18.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 18.
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18.3 Block Diagram Figure 18-1.
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18.4 I/O Lines Description Table 18-1. I/O Lines Description Name Description Type WKUP0 Wake-up 0 input Input SHDN Shutdown output Output 18.5 Product Dependencies 18.5.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller.
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18.6 Functional Description The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any pushbuttons or signal that wake up the system.
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18.7 Shutdown Controller (SHDWC) User Interface Table 18-2.
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18.7.1 Shutdown Control Register Name: SHDW_CR Address: 0xFFFFFE10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SHDW • SHDW: Shutdown Command 0 = No effect. 1 = If KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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18.7.2 Shutdown Mode Register Name: SHDW_MR Address: 0xFFFFFE14 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWKEN 16 – 15 14 13 12 11 – 10 – 9 3 – 2 – 1 – 7 6 5 4 CPTWK0 8 – 0 WKMODE0 • WKMODE0: Wake-up Mode 0 WKMODE[1:0] Wake-up Input Transition Selection 0 0 None.
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18.7.3 Shutdown Status Register Name: SHDW_SR Address: 0xFFFFFE18 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWK 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WAKEUP0 • WAKEUP0: Wake-up 0 Status 0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
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19. General Purpose Backup Registers (GPBR) 19.1 Description The System Controller embeds Four General-purpose Backup Registers. 19.
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19.3 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset 0x0 ... 0xc Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 3 SYS_GPBR3 Access Reset Read-write – ... ... Read-write – 19.3.
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20. Slow Clock Controller (SCKC) 20.1 Description The System Controller embeds a Slow Clock Controller. The slow clock can be generated either by an external 32768 Hz crystal oscillator or by the on-chip 32 kHz RC oscillator. The 32768 Hz crystal oscillator can be bypassed by setting the OSC32BYP bit to accept an external slow clock on XIN32.
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20.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator To switch from the internal 32 kHz RC oscillator to the 32768 Hz crystal oscillator, the programmer must execute the following sequence: z Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller. z Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1. z Wait 32768 Hz Startup Time for clock stabilization (software loop).
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20.4 Slow Clock Configuration (SCKC) User Interface Table 20-1.
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20.4.1 Slow Clock Configuration Register Name: SCKC_CR Address: 0xFFFFFE50 Access: Read-write Reset: 0x0000_0001 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCSEL 2 OSC32BYP 1 OSC32EN 0 RCEN • RCEN: Internal 32 kHz RC Oscillator 0: 32 kHz RC oscillator is disabled. 1: 32 kHz RC oscillator is enabled. • OSC32EN: 32768 Hz Oscillator 0: 32768 Hz oscillator is disabled.
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21. Clock Generator (CKGR) 21.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 22.13 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 21.
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21.3 CKGR Block Diagram Figure 21-1.
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21.4 Slow Clock Selection The slow clock can be generated either by an external 32768 Hz crystal or by the on-chip 32 kHz RC oscillator. The 32768 Hz crystal oscillator can be bypassed by setting the OSC32BYP bit to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1, respectively, the RCEN bit and the OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source. Figure 21-2.
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21.4.3 Switch from the 32768 Hz Crystal to Internal 32 kHz RC Oscillator The same procedure must be followed to switch from a 32768 Hz crystal to the internal 32 kHz RC oscillator. z Switch the master clock to a source different from slow clock (PLL or Main Oscillator). z Enable the internal 32 kHz RC oscillator for low power by setting the bit RCEN to 1 z Wait internal 32 kHz RC Startup Time for clock stabilization (software loop).
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21.4.
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21.5 Main Clock Figure 21-3.
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21.6 Main Clock Selection The main clock can be generated either by an external 12 MHz crystal oscillator or by the on-chip 12 MHz RC oscillator. This fast RC oscillator allows the processor to start or restart in a few microseconds when 12 MHz internal RC is selected. The 12 MHz crystal oscillator can be bypassed by setting the MOSCXTBY bit to accept an external main clock on XIN. Figure 21-4.
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21.6.2 Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal For USB operations an external 12 MHz crystal is required for better accuracy. The programmer controls the main clock switching by software and so must take precautions during the switching phase. To switch from internal 12 MHz RC oscillator to the 12 MHz crystal, the programmer must execute the following sequence: z Enable the 12 MHz oscillator by setting the bit MOSCXTEN to 1.
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counting down on the slow clock divided by 8 from the MOSCXTCNT value. Since the MOSCXTCNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor. 21.6.7 Main Clock Oscillator Selection The user can select either the 12 MHz Fast RC Oscillator or the 12 to 16 MHz Crystal Oscillator to be the source of Main Clock.
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21.7.1 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. The PLLA allows multiplication of the divider’s outputs.
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22. Power Management Controller (PMC) 22.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core. 22.2 Embedded Characteristics The Power Management Controller provides all the clock signals to the system.
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22.3 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler.
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22.4 Block Diagram Figure 22-2. General Clock Block Diagram PLLACK USBS UHP48M USBDIV+1 /4 UHP12M USB OHCI USB EHCI Prescaler /1,/2,/3,/4,...,/64 DDRCK X /1 /1.5 /2 2x MCK /1 /2 MCK /3 /4 Master Clock Controller SLCK MAINCK int /2 Divider MAINCK SLCK PCK Processor Clock Controller UPLLCK Peripherals Clock Controller ON/OFF Divider Periph_clk[..] ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] UPLLCK Programmable Clock Controller 22.
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22.6 USB Device and Host Clocks The USB Device and Host High Speed ports clocks are controlled by the UDPHS and UHPHS bits in PMC_PCER. To save power on this peripheral when they are is not used, the user can set these bits in PMC_PCDR. The UDPHS and UHPHS bits in PMC_PCR give the activity of these clocks. The PMC also provides the clocks UHP48M and UHP12M to the USB Host OHCI. The USB Host OHCI clocks are controlled by the UHP bit in PMC_SCER.
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22.10 Programmable Clock Output Controller The PMC controls 2 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock, the Master Clock, the PLLACK/PLLADIV2, the UTMI PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
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3. Setting Bias and High Speed PLL (UPLL) for UTMI The UTMI PLL is enabled by setting the UPLLEN field in the CKGR_UCKR register. The UTMI Bias must is enabled by setting the BIASEN field in the CKGR_UCKR register in the same time. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the PLLCOUNT field in the CKGR_UCKR register. Once this register has been correctly configured, the user must wait for LOCKU field in the PMC_SR register to be set.
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Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1) The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 5. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 2 programmable clocks can be enabled or disabled.
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22.12 Clock Switching Details 22.12.1 Master Clock Switching Timings Table 22-1 and Table 22-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 22-1. Clock Switching Timings (Worst Case) Fro m Main Clock SLCK PLL Clock Main Clock – 4 x SLCK + 2.5 x Main Clock SLCK 0.
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22.12.2 Clock Switching Waveforms Figure 22-3. Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 22-4.
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Figure 22-5. Change PLLA Programming Slow Clock PLLA Clock LOCKA MCKRDY Master Clock Slow Clock Write CKGR_PLLAR Figure 22-6.
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22.13 Power Management Controller (PMC) User Interface Table 22-3. Register Mapping Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only N.A. 0x0004 System Clock Disable Register PMC_SCDR Write-only N.A. 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0005 0x0010 Peripheral Clock Enable Register PMC _PCER Write-only N.A.
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22.13.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0xFFFFFC00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – SMDCK LCDCK DDRCK – – • DDRCK: DDR Clock Enable 0 = No effect. 1 = Enables the DDR clock. • LCDCK: LCD Clock Enable 0 = No effect. 1 = Enables the LCD clock.
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22.13.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0xFFFFFC04 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – SMDCK LCDCK DDRCK – PCK • PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode. • DDRCK: DDR Clock Disable 0 = No effect.
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22.13.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0xFFFFFC08 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – SMDCK LCDCK DDRCK – PCK • PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled. • DDRCK: DDR Clock Status 0 = The DDR clock is disabled.
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22.13.4 PMC Peripheral Clock Enable Register Name: PMC_PCER Address: 0xFFFFFC10 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0 = No effect.
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22.13.5 PMC Peripheral Clock Disable Register Name: PMC_PCDR Address: 0xFFFFFC14 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Disable 0 = No effect.
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22.13.
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22.13.7 PMC UTMI Clock Configuration Register Name: CKGR_UCKR Address: 0xFFFFFC1C Access: Read-write 31 30 29 28 27 – 26 – 25 – 24 BIASEN 21 20 19 – 18 – 17 – 16 UPLLEN BIASCOUNT 23 22 UPLLCOUNT 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • UPLLEN: UTMI PLL Enable 0 = The UTMI PLL is disabled. 1 = The UTMI PLL is enabled. When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
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22.13.8 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0xFFFFFC20 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 CFDEN 24 MOSCSEL 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 – 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 – 5 – 4 – • KEY: Password Should be written at value 0x37. Writing any other value in this field aborts the write operation.
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22.13.9 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0xFFFFFC24 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINFRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled.
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22.13.10PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read-write 31 – 30 – 29 1 28 – 23 22 21 20 27 – 26 25 MULA 24 19 18 17 16 10 9 8 2 1 0 MULA 15 14 13 12 11 OUTA 7 PLLACOUNT 6 5 4 3 DIVA Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
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22.13.
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22.13.12PMC USB Clock Register Name: PMC_USB Address: 0xFFFFFC38 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – USBDIV 7 6 5 4 3 2 1 0 – – – – – – – USBS • USBS: USB OHCI Input Clock Selection 0 = USB Clock Input is PLLA 1 = USB Clock Input is UPLL • USBDIV: Divider for USB OHCI Clock.
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22.13.13PMC SMD Clock Register Name: PMC_SMD Address: 0xFFFFFC3C Access : Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – SMDDIV 7 6 5 4 3 2 1 0 – – – – – – – SMDS • SMDS: SMD input clock selection 0 = SMD Clock Input is PLLA 1 = SMD Clock Input is UPLL • SMDDIV: Divider for SMD Clock.
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22.13.
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22.13.
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22.13.
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22.13.17PMC Status Register Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – FOS CFDS CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 – – – – – – PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 OSCSELS LOCKU – – MCKRDY – LOCKA MOSCXTS • MOSCXTS: Main XTAL Oscillator Status 0 = Main XTAL oscillator is not stabilized. 1 = Main XTAL oscillator is stabilized.
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• CFDEV: Clock Failure Detector Event 0 = No clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. 1 = At least one clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. • CFDS: Clock Failure Detector Status 0 = A clock failure of the main on-chip RC oscillator clock is not detected. 1 = A clock failure of the main on-chip RC oscillator clock is detected.
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22.13.
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22.13.
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22.13.20PMC Write Protect Mode Register Name: PMC_WPMR Address: 0xFFFFFCE4 Access: Read-write Reset: See Table 22-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
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22.13.21PMC Write Protect Status Register Name: PMC_WPSR Address: 0xFFFFFCE8 Access: Read-only Reset: See Table 22-3 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register.
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22.13.22PMC Peripheral Control Register Name: PMC_PCR Address: 0xFFFFFD0C Access: Read-write 31 — 30 — 29 — 28 EN 27 — 26 — 25 — 24 — 23 — 22 — 21 — 20 — 19 — 18 — 17 15 — 14 — 13 — 12 CMD 11 — 10 — 9 — 8 — 7 — 6 — 5 4 3 2 1 0 16 DIV PID • PID: Peripheral ID Only the following Peripheral IDs can have a DIV value other than 0: PID2, PID3, PID5 to PID11, PID13 to PID19, PID28 to PID30.
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23. Parallel Input/Output (PIO) Controller 23.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
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23.3 Block Diagram Figure 23-1. Block Diagram PIO Controller Interrupt Controller PIO Interrupt PIO Clock PMC Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 23-2.
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23.4 Product Dependencies 23.4.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
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23.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 23-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 23-3.
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23.5.1 Pull-up and Pull-down Resistor Control Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
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After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. 23.5.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral.
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Figure 23-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 23.5.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.
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The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals.
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These Additional Modes are: z Rising Edge Detection z Falling Edge Detection z Low Level Detection z High Level Detection In order to select an Additional Interrupt Mode: z The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR (Edge Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level Detection. The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status Register).
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z Rising edge on PIO line 7 z Any edge on the other lines The configuration required is described below. 23.5.10.2Interrupt Mode Configuration All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. 23.5.10.3Edge or Level Detection Configuration Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR.
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Only PADs PA[20:15], PA[13:11] and PA[4:2] can be configured. When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. When programming 0xF in fields, the propagation delay of the corresponding pad is maximal. Figure 23-9. Programmable I/O Delays PAin[0] PIO PAout[0] Programmable Delay Line DELAY1 PAin[1] PAout[1] Programmable Delay Line DELAY2 PAin[2] PAout[2] Programmable Delay Line DELAYx 23.5.
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z “PIO Pull Up Enable Register” on page 235 z “PIO Peripheral ABCD Select Register 1” on page 237 z “PIO Peripheral ABCD Select Register 2” on page 238 z “PIO Output Write Enable Register” on page 243 z “PIO Output Write Disable Register” on page 243 z “PIO Pad Pull Down Disable Register” on page 241 z “PIO Pad Pull Down Status Register” on page 242 SAM9G15 [DATASHEET] 11052D–ATARM–31-Oct-12 220
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23.6 I/O Lines Programming Example The programing example as shown in Table 23-1 below is used to obtain the following configuration.
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23.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is notmultiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 23-2.
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Table 23-2.
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Table 23-2. Register Mapping (Continued) Offset Register Name 0x0118 I/O Drive Register 2 PIO_DRIVER2 0x011C Reserved 0x0120 to 0x014C Reserved Access Reset Read-write 0x00000000 Notes: 1. Reset value depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines.
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23.7.
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23.7.3 PIO Status Register Name: PIO_PSR Address: 0xFFFFF408 (PIOA), 0xFFFFF608 (PIOB), 0xFFFFF808 (PIOC), 0xFFFFFA08 (PIOD) Access: ead-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active).
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23.7.
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23.7.
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23.7.
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23.7.11 PIO Clear Output Data Register Name: PIO_CODR Address: 0xFFFFF434 (PIOA), 0xFFFFF634 (PIOB), 0xFFFFF834 (PIOC), 0xFFFFFA34 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Clear Output Data 0: No effect.
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23.7.13 PIO Pin Data Status Register Name: PIO_PDSR Address: 0xFFFFF43C (PIOA), 0xFFFFF63C (PIOB), 0xFFFFF83C (PIOC), 0xFFFFFA3C (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The I/O line is at level 0.
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23.7.15 PIO Interrupt Disable Register Name: PIO_IDR Address: 0xFFFFF444 (PIOA), 0xFFFFF644 (PIOB), 0xFFFFF844 (PIOC), 0xFFFFFA44 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0: No effect.
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23.7.
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23.7.
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23.7.
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23.7.23 PIO Pull Up Status Register Name: PIO_PUSR Address: 0xFFFFF468 (PIOA), 0xFFFFF668 (PIOB), 0xFFFFF868 (PIOC), 0xFFFFFA68 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0: Pull Up resistor is enabled on the I/O line.
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23.7.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read-write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” . • P0-P31: Peripheral Select.
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23.7.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Access: Read-write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” . • P0-P31: Peripheral Select.
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23.7.26 PIO Input Filter Slow Clock Disable Register Name: PIO_IFSCDR Address: 0xFFFFF480 (PIOA), 0xFFFFF680 (PIOB), 0xFFFFF880 (PIOC), 0xFFFFFA80 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Clock Glitch Filtering Select. 0: No Effect.
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23.7.35 PIO Output Write Status Register Name: PIO_OWSR Address: 0xFFFFF4A8 (PIOA), 0xFFFFF6A8 (PIOB), 0xFFFFF8A8 (PIOC), 0xFFFFFAA8 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0: Writing PIO_ODSR does not affect the I/O line.
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23.7.37 PIO Additional Interrupt Modes Disable Register Name: PIO_AIMDR Address: 0xFFFFF4B4 (PIOA), 0xFFFFF6B4 (PIOB), 0xFFFFF8B4 (PIOC), 0xFFFFFAB4 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Additional Interrupt Modes Disable. 0: No effect.
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23.7.39 PIO Edge Select Register Name: PIO_ESR Address: 0xFFFFF4C0 (PIOA), 0xFFFFF6C0 (PIOB), 0xFFFFF8C0 (PIOC), 0xFFFFFAC0 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge Interrupt Selection. 0: No effect.
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23.7.41 PIO Edge/Level Status Register Name: PIO_ELSR Address: 0xFFFFF4C8 (PIOA), 0xFFFFF6C8 (PIOB), 0xFFFFF8C8 (PIOC), 0xFFFFFAC8 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge/Level Interrupt source selection.
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23.7.43 PIO Rising Edge/High Level Select Register Name: PIO_REHLSR Address: 0xFFFFF4D4 (PIOA), 0xFFFFF6D4 (PIOB), 0xFFFFF8D4 (PIOC), 0xFFFFFAD4 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Rising Edge /High Level Interrupt Selection.
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23.7.45 PIO Lock Status Register Name: PIO_LOCKSR Address: 0xFFFFF4E0 (PIOA), 0xFFFFF6E0 (PIOB), 0xFFFFF8E0 (PIOC), 0xFFFFFAE0 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Lock Status. 0: The I/O line is not locked. 1: The I/O line is locked.
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23.7.46 PIO Write Protect Mode Register Name: PIO_WPMR Address: 0xFFFFF4E4 (PIOA), 0xFFFFF6E4 (PIOB), 0xFFFFF8E4 (PIOC), 0xFFFFFAE4 (PIOD) Access: Read-write Reset: See Table 23-2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – – – For more information on Write Protection Registers, refer to Section 23.7 ”Parallel Input/Output Controller (PIO) User Interface”.
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23.7.47 PIO Write Protect Status Register Name: PIO_WPSR Address: 0xFFFFF4E8 (PIOA), 0xFFFFF6E8 (PIOB), 0xFFFFF8E8 (PIOC), 0xFFFFFAE8 (PIOD) Access: Read-only Reset: See Table 23-2 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 – WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – – – • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the PIO_WPSR register.
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23.7.
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23.7.50 PIO I/O Drive Register 1 Name: PIO_DRIVER1 Address: 0xFFFFF514 (PIOA), 0xFFFFF714 (PIOB), 0xFFFFF914 (PIOC), 0xFFFFFB14 (PIOD) Access: Read-write Reset: 0x0 31 30 29 LINE15 23 22 21 LINE11 15 28 14 20 13 19 6 12 5 18 11 17 9 8 LINE4 2 LINE1 16 LINE8 10 3 24 LINE12 LINE5 4 LINE2 25 LINE9 LINE6 LINE3 26 LINE13 LINE10 LINE7 7 27 LINE14 1 0 LINE0 • LINEx [x=0..
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23.7.51 PIO I/O Drive Register 2 Name: PIO_DRIVER2 Address: 0xFFFFF518 (PIOA), 0xFFFFF718 (PIOB), 0xFFFFF918 (PIOC), 0xFFFFFB18 (PIOD) Access: Read-write Reset: 0x0 31 30 29 LINE31 23 22 21 LINE27 15 27 14 20 13 19 6 12 5 18 11 17 9 8 LINE20 2 LINE17 16 LINE24 10 3 24 LINE28 LINE21 4 LINE18 25 LINE25 LINE22 LINE19 26 LINE29 LINE26 LINE23 7 28 LINE30 1 0 LINE16 • LINEx [x=16..
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24. Debug Unit (DBGU) 24.1 Description The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARMbased systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication.
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24.3 Block Diagram Figure 24-1. Debug Unit Functional Block Diagram Peripheral Bridge (Peripheral) DMA Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive DRXD COMMRX ARM Processor COMMTX DCC Handler Chip ID nTRST ICE Access Handler Interrupt Control dbgu_irq Power-on Reset force_ntrst Table 24-1.
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24.4 Product Dependencies 24.4.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. Table 24-2. I/O Lines Instance Signal I/O Line Peripheral DBGU DRXD PA9 A DBGU DTXD PA10 A 24.4.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller.
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Figure 24-3. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 24.5.2 Receiver 24.5.2.1 Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
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Figure 24-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 24.5.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 24-6.
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24.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 24-9.
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When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. Figure 24-11.Transmitter Control DBGU_THR Data 0 Data 1 Shift Register DTXD Data 0 S Data 0 Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 24.5.
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Figure 24-12.Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter TXD VDD Disabled Disabled RXD TXD 24.5.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
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z ARCH - identifies the set of embedded peripherals z SRAMSIZ - indicates the size of the embedded SRAM z EPROC - indicates the embedded ARM processor z VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 24.5.8 ICE Access Prevention The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface.
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24.6 Debug Unit (DBGU) User Interface Table 24-3.
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24.6.1 Debug Unit Control Register Name: DBGU_CR Address: 0xFFFFF200 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
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24.6.6 Debug Unit Status Register Name: DBGU_SR Address: 0xFFFFF214 Access: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
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24.6.7 Debug Unit Receiver Holding Register Name: DBGU_RHR Address: 0xFFFFF218 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set. 24.6.
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24.6.
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24.6.10 Debug Unit Chip ID Register Name: DBGU_CIDR Address: 0xFFFFF240 Access: Read-only 31 30 29 EXT 23 28 27 26 NVPTYP 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 EPROC 3 2 VERSION • VERSION: Version of the Device Values depend upon the version of the device.
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Value Name Description 13 – Reserved 14 2048K 2048K bytes 15 – Reserved • NVPSIZ2 Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8K bytes 2 16K 16K bytes 3 32K 32K bytes 4 – Reserved 5 64K 64K bytes 6 Reserved 7 128K 128K bytes 8 – Reserved 9 256K 256K bytes 10 512K 512K bytes 11 – Reserved 12 1024K 1024K bytes 13 – Reserved 14 2048K 2048K bytes 15 – Reserved • SRAMSIZ: Internal SRAM Size Value Name Description
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Value Name Description 13 256K 256K bytes 14 96K 96K bytes 15 512K 512K bytes • ARCH: Architecture Identifier Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x40 AT91x40 AT91x40 Series 0x42 AT91x42 AT91x42 Series 0x55 AT91x55 AT91x55 Series 0x60 AT91SAM7Axx AT91SAM7Axx Series 0x61 AT91SAM7AQxx AT91SAM7AQxx Series 0x63
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Value Name Description 0x9A ATSAM3SDxC ATSAM3SDxC Series (100-pin version) 0xA5 – Reserved 0xF0 AT75Cxx AT75Cxx Series • NVPTYP: Nonvolatile Program Memory Type Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on-chip Flash 4 SRAM SRAM emulating ROM 2 FLASH Embedded Flash Memory 3 ROM_FLASH ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size • EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exist
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24.6.11 Debug Unit Chip ID Extension Register Name: DBGU_EXID Address: 0xFFFFF244 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
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24.6.12 Debug Unit Force NTRST Register Name: DBGU_FNR Address: 0xFFFFF248 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST • FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor’s TAP controller is held low.
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25. Bus Matrix (MATRIX) 25.1 Description The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
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25.2.2 Matrix Slaves The Bus Matrix manages 9 slaves. Each slave has its own arbiter, thus allowing a different arbitration per slave to be programmed. Table 25-2.
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25.3 Memory Mapping The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. Each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible. The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR), that performs remap action for every master independently. 25.
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This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-privileged masters will get one latency cycle. This technique is useful for a master that mainly performs single accesses or short bursts with Idle cycles in between.
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Use of undefined length16-beat bursts, or less, is discouraged since this generally decreases significantly overall bus bandwidth due to arbitration and slave latencies at each first access of a burst.
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25.5.2.1 Fixed Priority Arbitration Fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct priority pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority pools).
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25.7 Bus Matrix (MATRIX) User Interface Table 25-4.
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Table 25-4.
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25.7.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0...
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25.7.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...
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25.7.3 Bus Matrix Priority Registers A For Slaves Name: MATRIX_PRAS0...
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25.7.4 Bus Matrix Priority Registers B For Slaves Name: MATRIX_PRBS0...
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25.7.
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25.7.6 Chip Configuration User Interface Table 25-5.
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25.7.6.1 EBI Chip Select Assignment Register Name: CCFG_EBICSA Access: Read-write Reset: 0x0000_0000 31 30 29 28 27 26 25 24 – – – – – – DDR_MP_EN NFD0_ON_D16 23 22 21 20 19 18 17 16 – – – – – – EBI_DRIVE – 15 14 13 12 11 10 9 8 – – – – – – EBI_DBPDC EBI_DBPUC 7 6 5 4 3 2 1 0 – – – – EBI_CS3A – EBI_CS1A – • EBI_CS1A: EBI Chip Select 1 Assignment 0 = EBI Chip Select 1 is assigned to the Static Memory Controller.
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Table 25-6. Connection examples with various VDDNF and VDDIOM NFD0_ON_D1 6 Signals VDDIOM VDDNF External Memory 0 NFD0 = D0, ..., NFD15 = D15 1.8V 1.8V DDR2 or LPDDR or LPSDR + NAND Flash 1.8V 0 NFD0 = D0, ..., NFD15 = D15 3.3V 3.3V 32-bit SDR + NAND Flash 3.3V 1 NFD0 = D16, ..., NFD15 = D31 1.8V 1.8V DDR2 or LPDDR or LPSDR + NAND Flash 1.8V 1 NFD0 = D16, ..., NFD15 = D31 1.8V 3.3V DDR2 or LPDDR or LPSDR + NAND Flash 3.3V 1 NFD0 = D16, ..., NFD15 = D31 3.3V 1.
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25.7.7 Write Protect Mode Register Name: MATRIX_WPMR Address: 0xFFFFDFE4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN For more details on MATRIX_WPMR, refer to Section 25.6 “Write Protect Registers” on page 284. • WPEN: Write Protect ENable 0 = Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
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25.7.8 Write Protect Status Register Name: MATRIX_WPSR Address: 0xFFFFDFE8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS For more details on MATRIX_WPSR, refer to Section 25.6 “Write Protect Registers” on page 284. • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR.
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26. External Bus Interface (EBI) 26.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, DDR, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, DDR2 and SDRAM.
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26.
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26.3 EBI Block Diagram Figure 26-1.
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26.4 I/O Lines Description Table 26-1.
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26.5 Application Example 26.5.1 Hardware Interface Table 26-3 on page 301 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 26-3.
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Table 26-4.
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Table 26-4. EBI Pins and External Device Connections Signals: EBI_ Power supply Pins of the Interfaced Device DDR2/LPDDR SDR/LPSDR NAND Flash DDRC SDRAMC NFC Controller SDWE VDDIOM WE WE – Pxx VDDNF – – CE VDDNF – – RDY Pxx Note: 1. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D7 or D16-D24 depending on memory power supplies. This switch is located in the EBICSA register in the Bus Matrix user interface. 26.5.2 Product Dependencies 26.5.2.
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To improve EMI, programmable delay has been inserted on lines able to run at high speed. The control of these delays is as follows: z EBI (DDR2SDRC\SMC\NAND Flash) D[15:0] controlled by 2 registers DELAY1 and DELAY2 located in the SMC user interface. z D[0] <=> DELAY1[3:0], z D[1] <=> DELAY1[7:4],..., z D[6] <=> DELAY1[27:24], z D[7] <=> DELAY1[31:28] z D[8] <=> DELAY2[3:0], z D[9] <=> DELAY2[7:4],...
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In the following example the NAND Flash and the external RAM (DDR2 or LP-DDR or 16-bit LP-SDR) are in the same power supply range, (NFD0_ON_D16 = default). DDR2 or LP-DDR or 16-bit LP-SDR (1.8V) D[15:0] D[15:0] NAND Flash (1.8V) D[15:0] A[22:21] ALE CLE EBI 32bit SDRAM (3.3V) D[15:0] D[31:16] D[15:0] D[31:16] NAND Flash (3.
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It is controlled by DDR_MP_EN bit in EBI Chip Select Assignment Register. Figure 26-2. DDR2SDRC Multi-port Enabled (DDR_MP_EN = 1) DDR2SDRC Port 3 Port 2 Port 1 DDR2 or LP-DDR Device Bus Matrix Port 0 NAND Flash Device EBI Figure 26-3. DDR2SDRC Multi-port Disabled (DDR_MP_EN = 0) DDR2SDRC not used not used not used (LP-)SDR Device Bus Matrix Port 0 NAND Flash Device EBI 26.5.3.7 Programmable Multi-bit ECC Controller For information on the PMECC Controller, refer to the PMECC section. 26.5.3.
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Figure 26-4.
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26.5.4 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 26.5.4.1 2x8-bit DDR2 on EBI Hardware Configuration Software Configuration z Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Register located in the bus matrix memory space. z Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency.
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26.5.4.2 16-bit LPDDR on EBI Hardware Configuration Software Configuration The following configuration has to be performed: z Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip Select Register located in the bus matrix memory space. z Initialize the DDR2 Controller depending on the LP-DDR device and system bus frequency. The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initialization” in “DDR/SDR SDRAM Controller (DDRSDRC)”.
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26.5.4.3 16-bit SDRAM on EBI Hardware Configuration Software Configuration The following configuration has to be performed: z Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. z Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits.
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26.5.4.4 2x16-bit SDRAM on EBI Hardware Configuration A[1..14] D[0..31] SDRAM MN1 VDDIOM A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 23 24 25 26 29 30 31 32 33 34 22 35 BA0 BA1 20 21 A14 36 40 CKE 37 CLK 38 DQM0 DQM1 15 39 CAS RAS 17 18 WE 16 19 R1 470K MN2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.
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26.5.4.5 8-bit NAND Flash with NFD0_ON_D16 = 0 Hardware Configuration D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
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26.5.4.6 16-bit NAND Flash with NFD0_ON_D16 = 0 Hardware Configuration D[0..15] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C 10K MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.
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26.5.4.7 8-bit NAND Flash with NFD0_ON_D16 = 1 Hardware Configuration Software Configuration The following configuration has to be performed: z Set NFD0_ON_D16 = 1 in the EBI Chip Select Assignment Register located in the bus matrix memory space z Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register z Reserve A21 / A22 for ALE / CLE functions.
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26.5.4.8 16-bit NAND Flash with NFD0_ON_D16 = 1 Hardware Configuration Software Configuration The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller.
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26.5.4.9 NOR Flash on NCS0 Hardware Configuration D[0..15] A[1..
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27. Programmable Multibit ECC Controller (PMECC) 27.1 Description The Programmable Multibit ECC Controller (PMECC) is a programmable binary BCH (Bose, Chaudhuri and Hocquenghem) encoder/decoder. This controller can be used to generate redundancy information for both Single-Level Cell (SLC) and Multi-level Cell (MLC) NAND Flash devices. It supports redundancy for correction of 2, 4, 8, 12 or 24 bits of error per sector of data. 27.
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27.3 Block Diagram Figure 27-1.
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27.4 Functional Description The NAND Flash sector size is programmable and can be set to 512 bytes or 1024 bytes. The PMECC module generates redundancy at encoding time, when a NAND write page operation is performed. The redundancy is appended to the page and written in the spare area. This operation is performed by the processor. It moves the content of the PMECCx registers into the NAND Flash memory.
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Figure 27-2.
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27.4.1 MLC/SLC Write Page Operation using PMECC When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR field of the PMECCFG register set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error protected, then the SPAREEN bit of the PMECCFG register is set to one. When the NAND spare area contains only redundancy information, the SPAREEN bit is set to zero.
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27.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set When the SPAREEN field of the PMECC_CFG register is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When the encoding process is over, the redundancy is written to the spare area in user mode, USER field of the PMECC_CTRL must be set to one. Figure 27-3.
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27.4.2 MLC/SLC Read Page Operation using PMECC Table 27-3.
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27.4.2.2 MLC/SLC Read Operation If the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When AUTO field is set to one the ECC is retrieved automatically, otherwise the ECC must be read using user mode. Figure 27-6.
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27.5 Software Implementation 27.5.1 Remainder Substitution Procedure The substitute function evaluates the polynomial remainder, with different values of the field primitive elements. The finite field arithmetic addition operation is performed with the Exclusive or. The finite field arithmetic multiplication operation is performed through the gf_log, gf_antilog lookup tables. The REM2NP1 and REMN2NP3 fields of the PMECC_REMx registers contain only odd remainders.
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int i; int j; int k; /* mu */ int mu[NB_ERROR_MAX+2]; /* sigma ro */ int sro[2*NB_ERROR_MAX+1]; /* discrepancy */ int dmu[NB_ERROR_MAX+2]; /* delta order */ int delta[NB_ERROR_MAX+2]; /* index of largest delta */ int ro; int largest; int diff; /* */ /* First Row */ /* */ /* Mu */ mu[0] = -1; /* Actually -1/2 */ /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[0][i] = 0; smu[0][0] = 1; /* discrepancy set to 1 */ dmu[0] = 1; /* polynom order set to 0 */ lmu[0] = 0; /* delta set to -1 */ de
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/* copy previous polynom order to the next */ lmu[i+1] = lmu[i]; } else { ro = 0; largest = -1; /* find largest delta with dmu != 0 */ for (j=0; j largest) { largest = delta[j]; ro = j; } } } /* initialize signal ro */ for (k = 0; k < 2*NB_ERROR_MAX+1; k ++) { sro[k] = 0; } /* compute difference */ diff = (mu[i] - mu[ro]); /* compute X ^ (2(mu-ro)) */ for (k = 0; k < (2*NB_ERROR_MAX+1); k ++) { sro[k+diff] = smu[ro][k]; } /* multiply by dmu * dmu[ro]^-1 */ for (k = 0;
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delta[i+1] = (mu[i+1] * 2 - lmu[i+1]) >> 1; /* In either case compute the discrepancy */ for (k = 0 ; k <= (lmu[i+1]>>1); k++) { if (k == 0) dmu[i+1] = si[2*(i-1)+3]; /* check if one operand of the multiplier is null, its index is -1 */ else if (smu[i+1][k] && si[2*(i-1)+3-k]) dmu[i+1] = gf_antilog[(gf_log[smu[i+1][k]] + gf_log[si[2*(i-1)+3-k]])%nn] ^ dmu[i+1]; } } return 0; } 27.5.3 Find the Error Position The output of the get_sigma() procedure is a polynomial stored in the smu[NB_ERROR+1][] table.
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27.6 Programmable Multibit ECC Controller (PMECC) User Interface Table 27-4.
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Table 27-4.
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27.6.
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– for NAND read access: 0: The spare area is skipped. 1: The spare area contains protected data or only redundancy information. • AUTO: Automatic Mode Enable This bit is only relevant in NAND Read Mode, when spare enable is activated. 0: Indicates that the spare area is not protected. In that case the ECC computation takes into account the ECC area located in the spare area. (within the start address and the end address). 1: Indicates that the spare is error protected.
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27.6.2 PMECC Spare Area Size Register Name: PMECC_SAREA Address: 0xFFFFE004 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 SPARESIZE 0 SPARESIZE • SPARESIZE: Spare Area Size The spare area size is equal to (SPARESIZE+1) bytes.
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27.6.3 PMECC Start Address Register Name: PMECC_SADDR Address: 0xFFFFE008 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 STARTADDR 0 STARTADDR • STARTADDR: ECC Area Start Address (byte oriented address) This field indicates the first byte address of the ECC area. Location 0 matches the first byte of the spare area.
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27.6.4 PMECC End Address Register Name: PMECC_EADDR Address: 0xFFFFE00C Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 3 2 1 24 – 16 – 8 ENDADDR 0 ENDADDR • ENDADDR: ECC Area End Address (byte oriented address) This field indicates the last byte address of the ECC area.
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27.6.5 PMECC Clock Control Register Name: PMECC_CLK Address: 0xFFFFE010 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 25 – 17 – 9 – 1 CLKCTRL 24 – 16 – 8 – 0 • CLKCTRL: Clock Control Register The PMECC Module data path Setup Time is set to CLKCTRL+1. This field indicates the database setup times in number of clock cycles.
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27.6.6 PMECC Control Register Name: PMECC_CTRL Address: 0xFFFFE014 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DISABLE 28 – 20 – 12 – 4 ENABLE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 USER 25 – 17 – 9 – 1 DATA 24 – 16 – 8 – 0 RST • RST: Reset the PMECC Module When set to one, this bit reset PMECC controller, configuration registers remain unaffected.
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27.6.7 PMECC Status Register Name: PMECC_SR Address: 0xFFFFE018 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 ENABLE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 BUSY • BUSY: The Kernel of the PMECC is Busy • ENABLE: PMECC Module Status 0: The PMECC Module is disabled and can be configured. 1: The PMECC Module is enabled and the configuration registers cannot be written.
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27.6.
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27.6.
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27.6.
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27.6.11 PMECC Interrupt Status Register Name: PMECC_ISR Address: 0xFFFFE028 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 ERRIS • ERRIS: Error Interrupt Status Register When set to one, bit i of the PMECCISR register indicates that sector i is corrupted.
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27.6.12 PMECC ECC x Register Name: PMECC_ECCx [x=0..10] [sec_num=0..7] Address: 0xFFFFE040 [0][0] .. 0xFFFFE068 [10][0] 0xFFFFE080 [0][1] .. 0xFFFFE0A8 [10][1] 0xFFFFE0C0 [0][2] .. 0xFFFFE0E8 [10][2] 0xFFFFE100 [0][3] .. 0xFFFFE128 [10][3] 0xFFFFE140 [0][4] .. 0xFFFFE168 [10][4] 0xFFFFE180 [0][5] .. 0xFFFFE1A8 [10][5] 0xFFFFE1C0 [0][6] .. 0xFFFFE1E8 [10][6] 0xFFFFE200 [0][7] ..
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27.6.13 PMECC Remainder x Register Name: PMECC_REMx [x=0..11] [sec_num=0..7] Address: 0xFFFFE240 [0][0] .. 0xFFFFE26C [11][0] 0xFFFFE280 [0][1] .. 0xFFFFE2AC [11][1] 0xFFFFE2C0 [0][2] .. 0xFFFFE2EC [11][2] 0xFFFFE300 [0][3] .. 0xFFFFE32C [11][3] 0xFFFFE340 [0][4] .. 0xFFFFE36C [11][4] 0xFFFFE380 [0][5] .. 0xFFFFE3AC [11][5] 0xFFFFE3C0 [0][6] .. 0xFFFFE3EC [11][6] 0xFFFFE400 [0][7] ..
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28. Programmable Multibit ECC Error Location Controller (PMERRLOC) 28.1 Description The PMECC Error Location Controller provides hardware acceleration for determining roots of polynomials over two finite fields: GF(2^13) and GF(2^14). It integrates 24 fully programmable coefficients. These coefficients belong to GF(2^13) or GF(2^14). The coefficient programmed in the PMERRLOC_SIGMAx register is the coefficient of degree x in the polynomial. 28.2 28.
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28.4 Functional Description The PMERRLOC search operation is started as soon as a write access is detected in the ELEN register and can be disabled by writing to the ELDIS register. The ENINIT field of the ELEN register shall be initialized with the number of Galois field elements to test. The set of the roots can be limited to a valid range. Table 28-1. ENINIT field value for a sector size of 512 bytes Error Correcting Capability ENINIT Value 2 4122 4 4148 8 4200 12 4252 24 4408 Table 28-2.
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28.5 Programmable Multibit ECC Error Location Controller (PMERRLOC) User Interface Table 28-3.
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28.5.1 Error Location Configuration Register Name: PMERRLOC_ELCFG Address: 0xFFFFE600 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 27 – 19 12 – 4 – 11 – 3 – 26 – 18 ERRNUM 10 – 2 – 25 – 17 24 – 16 9 – 1 – 8 – 0 SECTORSZ • ERRNUM: Number of Errors • SECTORSZ: Sector Size 0: The ECC computation is based on a 512-byte sector. 1: The ECC computation is based on a 1024-byte sector.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.10 Error Location SIGMAx Register Name: PMERRLOC_SIGMAx [x=0..24] Address: 0xFFFFE628 [0] .. 0xFFFFE688 [24] Access: Read-Write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 5 4 3 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 0 SIGMAx SIGMAx • SIGMAx: Coefficient of Degree x in the SIGMA Polynomial. SIGMAx belongs to the finite field GF(2^13) when the sector size is set to 512 bytes.
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28.5.11 PMECC Error Locationx Register Name: PMERRLOC_ELx [x=0..23] Address: 0xFFFFE68C Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 5 4 3 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 0 ERRLOCN ERRLOCN • ERRLOCN: Error Position within the Set {sector area, spare area}. ERRLOCN points to 0 when the first bit of the main area is corrupted.
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29. Static Memory Controller (SMC) 29.1 Description The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
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29.3 I/O Lines Description Table 29-1.
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29.5 Application Example 29.5.1 Hardware Interface Figure 29-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 D0 - D7 128K x 8 SRAM D8-D15 D0 - D7 CS NWR0/NWE A2 - A25 A2 - A18 A0 - A16 NRD OE NWR1/NBS1 WE 128K x 8 SRAM D16 - D23 D24-D31 D0 - D7 A0 - A16 NRD Static Memory Controller 29.
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29.7 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 29-2).
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Figure 29-3. Memory Connection for an 8-bit Data Bus D[7:0] D[7:0] A[18:2] A[18:2] SMC A0 A0 A1 A1 NWE Write Enable NRD Output Enable NCS[2] Memory Enable Figure 29-4. Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC A[0] NBS0 Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Memory Enable Figure 29-5.
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29.8.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. z For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
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29.8.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 29-3 shows signal multiplexing depending on the data bus width and the byte access type. For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused.
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29.9 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 29.9.
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29.9.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles.
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29.9.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation. 29.9.2.
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Figure 29-11.READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS tPACC D[31:0] Data Sampling 29.9.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 29-12. The write cycle starts with the address setting on the memory address bus. 29.9.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1.
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Figure 29-12.Write Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NWE_SETUP NCS_WR_SETUP NWE_PULSE NWE_HOLD NCS_WR_PULSE NCS_WR_HOLD NWE_CYCLE 29.9.3.3 Write Cycle The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change.
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Figure 29-13.Null Setup and Hold Values of NCS and NWE in Write Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] NWE_PULSE NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE NWE_CYCLE 29.9.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 29.9.
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Figure 29-14.WRITE_MODE = 1. The write operation is controlled by NWE MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 29.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 29-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal.
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29.9.5 Write Protected Registers To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write-protected by setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the SMC Write Protect Status Register (SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
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For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State” on page 375. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus.
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29.10.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select).
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Figure 29-18.Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD no hold no setup D[31:0] write cycle (WRITE_MODE = 0) Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) Figure 29-19.
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29.10.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State.
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29.11.1 READ_MODE Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS.
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Figure 29-21.TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS tpacc D[31:0] TDF = 3 clock cycles NCS controlled read operation 29.11.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
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Figure 29-22.TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK A[25:2] NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[31:0] read access on NCS0 (NRD controlled) Read to Write Wait State write access on NCS0 (NWE controlled) 29.11.3 TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins.
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Figure 29-23.TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[31:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 29-24.
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Figure 29-25.TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[31:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 29.12 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
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29.12.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 29-26.
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Figure 29-27.
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29.12.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 29-28 and Figure 29-29. After deassertion, the access is completed: the hold step of the access is performed.
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Figure 29-29.
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29.12.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
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29.13 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
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Figure 29-32.Clock Rate Transition Occurs while the SMC is Performing a Write Operation Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 1 1 1 1 1 3 2 2 NCS NWE_CYCLE = 3 NWE_CYCLE = 7 SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State Figure 29-33.
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29.14 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
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In page mode, the programming of the read timings is described in Table 29-7: Table 29-7. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
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Figure 29-35.
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29.15 Programmable IO Delays The external bus interface consists of a data bus, an address bus and control signals. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, SMC_DELAY1-8. The additional programmable delays for each IO range from 0 to 4 ns (Worst Case PVT).
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29.16 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 29-8. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 29-8, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 29-8.
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29.16.1 SMC Setup Register Name: SMC_SETUP[0..
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29.16.2 SMC Pulse Register Name: SMC_PULSE[0..
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29.16.3 SMC Cycle Register Name: SMC_CYCLE[0..5] Address: 0xFFFFEA08 [0], 0xFFFFEA18 [1], 0xFFFFEA28 [2], 0xFFFFEA38 [3], 0xFFFFEA48 [4], 0xFFFFEA58 [5] Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – NRD_CYCLE 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 – – – – – – – NWE_CYCLE 7 6 5 4 3 2 1 0 NWE_CYCLE • NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle.
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29.16.4 SMC MODE Register Name: SMC_MODE[0..5] Address: 0xFFFFEA0C [0], 0xFFFFEA1C [1], 0xFFFFEA2C [2], 0xFFFFEA3C [3], 0xFFFFEA4C [4], 0xFFFFEA5C [5] Access: Read-write 31 30 – – 23 22 21 20 – – – TDF_MODE 15 14 13 12 – – 7 6 – – 29 28 PS DBW 5 4 EXNW_MODE 27 26 25 24 – – – PMEN 19 18 17 16 TDF_CYCLES 11 10 9 8 – – – BAT 3 2 1 0 – – WRITE_MODE READ_MODE • READ_MODE: 1: The read operation is controlled by the NRD signal.
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• BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
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29.16.5 SMC DELAY I/O Register Name: SMC_DELAY 1-8 Address: 0xFFFFEAC0 [1] .. 0xFFFFEADC [8] Access: Read-write Reset: See Table 29-8 31 30 29 28 27 26 Delay8 23 22 21 20 19 18 Delay6 15 14 13 6 24 17 16 9 8 1 0 Delay5 12 11 10 Delay4 7 25 Delay7 Delay3 5 Delay2 4 3 2 Delay1 • Delay x: Gives the number of elements in the delay line.
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29.16.6 SMC Write Protect Mode Register Name: SMC_WPMR Address: 0xFFFFEAE4 Access: Read-write Reset: See Table 29-8 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
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29.16.7 SMC Write Protect Status Register Name: SMC_WPSR Address: 0xFFFFEAE8 Access: Read-only Reset: See Table 29-8 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register.
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30. DDR SDR SDRAM Controller (DDRSDRC) 30.1 Description The DDR SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol. The DDRSDRC extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRSDRAM device and external 16-bit DDR-SDRAM device.
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30.
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30.3 DDRSDRC Module Diagram Figure 30-1.
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30.4 Initialization Sequence The addresses given are for example purposes only. The real address depends on implementation in the product. 30.4.1 SDR-SDRAM Initialization The initialization sequence is generated by software. The SDR-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 30.7.8 on page 442). 2. Program the features of the SDR-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.
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4. An NOP command will be issued to the low-power DDR1-SDRAM. Program NOP command into the Mode Register, the application must set Mode to 1 in the Mode Register (see Section 30.7.1 on page 431). Perform a write access to any DDR1-SDRAM address to acknowledge this command. Now clocks which drive DDR1-SDRAM device are enabled. A minimum pause of 200 μs will be provided to precede any signal toggle. 5. An all banks precharge command is issued to the low-power DDR1-SDRAM.
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6. An Extended Mode Register set (EMRS2) cycle is issued to chose between commercial or high temperature operations. The application must set Mode to 5 in the Mode Register (see Section 30.7.1 on page 431) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0.
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19. A mode Normal command is provided. Program the Normal mode into Mode Register (see Section 30.7.1 on page 431). Perform a write access to any DDR2-SDRAM address to acknowledge this command. 20. Perform a write access to any DDR2-SDRAM address. 21. Write the refresh rate into the count field in the Refresh Timer register (see page 432). (Refresh rate = delay between refresh cycles). The DDR2-SDRAM device requires a refresh every 15.625 μs or 7.81 μs.
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Figure 30-2. Single Write Access, Row Closed, Low-power DDR1-SDRAM Device SDCLK Row a A[12:0] COMMAND BA[1:0] PRCHG NOP NOP col a ACT NOP WRITE NOP 00 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da Trp = 2 3 Db Trcd = 2 Figure 30-3.
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Figure 30-4. Single Write Access, Row Closed, SDR-SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] Row a NOP PRCHG NOP ACT Col a NOP WRITE BST NOP 00 3 DM[1:0] 0 D[31:0] 3 DaDb Trp = 2 Trcd = 2 Figure 30-5.
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Figure 30-6. Burst Write Access, Row Closed, DDR2-SDRAM Device SDCLK A[12:0] Row a COMMAND BA[1:0] NOP PRCHG NOP col a ACT NOP WRITE NOP 0 DQS[1:0] DM[1:0] 3 0 D [15:0] Da Db Dc Dd 3 De Df Dg Dh Trcd = 2 Trp = 2 Figure 30-7.
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Figure 30-8. Write Command Followed By a Read Command without Burst Write Interrupt, Low-power DDR1-SDRAM Device SDCLK A[12:0] col a COMMAND NOP BA[1:0] col a WRITE NOP READ BST NOP 0 DQS[1:0] DM[1:0] 3 0 D[15:0] 3 Da Db Dc Dd De Df Dg Dh Da Db Twrd = BL/2 +2 = 8/2 +2 = 6 Twr = 1 In the case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle prior to the read command to avoid writing invalid data.
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Figure 30-10.SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] col a Row a NOP PRCHG NOP ACT NOP WRITE NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da 3 Da Db Db Data masked twtr 30.5.2 SDRAM Controller Read Cycle The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance of the DDRSDRC.
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Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given read command. When the read command is issued, 8 columns are selected. All accesses for that burst take place within these eight columns, meaning that the burst wraps within these 8 columns if the boundary is reached. These 8 columns are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block.
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Figure 30-12.Single Read Access, Row Close, Latency = 3, DDR2-SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] NOP PRCHG NOP Row a Col a ACT NOP READ 0 DQS[1] DQS[0] DM[1:0] 3 D[15:0] Da Trp Db Latency = 2 Trcd Figure 30-13.
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Figure 30-14.Burst Read Access, Latency = 2, Low-power DDR1-SDRAM Devices SDCLK Col a A[12:0] COMMAND BA[1:0] NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Dc Dd De Da Db Dc Db Df Dg Dh Latency = 2 Figure 30-15.
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Figure 30-16.Burst Read Access, Latency = 2, SDR-SDRAM Devices SDCLK A[12:0] COMMAND BA[1:0] col a NOP READ NOP BST NOP 0 DQS[1:0] DM[3:0] F D[31:0] DaDb DcDd DeDf Dg Dh Latency = 2 30.5.3 Refresh (Auto-refresh Command) An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The DDRSDRC generates these auto-refresh commands periodically.
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PASR/DS/TCSR bits are updated before entry into self refresh mode if DDRSDRC does not share an external bus with another controller or during a refresh command, and a pending read or write access, if DDRSDRC does share an external bus with another controller. This type of update is a function of the UPD_MR bit (see Section 30.7.7 “DDRSDRC Low-power Register” on page 440).
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Figure 30-19.Self Refresh Mode Exit SDCLK A[12:0] COMMAND NOP VALID NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] DaDb Exit Self Refresh mode clock must be stable before exiting self refresh mode TXNRD/TXSRD TXSR TXSR (DDR device) (Low-power DDR1 device) (Low-power SDR, SDR-SDRAM device) Figure 30-20.
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Figure 30-21.Automatic Update During AUTO-REFRESH Command and SDRAM Access SDCLK A[12:0] COMMAND Pasr-Tcr-Ds NOP PRCHALL NOP ARFSH NOP MRS NOP ACT CKE BA[1:0] 0 0 2 Trp Trfc Tmrd Update Extended mode register 30.5.4.2 Power-down Mode This mode is activated by setting the low-power command bits [LPCB] to ‘10’. Power-down mode is used when no access to the SDRAM device is possible. In this mode, power consumption is greater than in self refresh mode.
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Figure 30-22.Power-down Entry/Exit, Timeout = 0 SDCLK A[12:0] COMMAND READ BST NOP READ CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Exit power down mode Entry power down mode 30.5.4.3 Deep Power-down Mode The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is activated, all internal voltage generators inside the device are stopped and all data is lost. This mode is activated by setting the low-power command bits [LPCB] to ‘11’.
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30.5.4.4 Reset Mode The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-power command bits (LPCB) to 11 and the clock frozen command bit (CLK_FR) to 1. When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. Before enabling this mode, the end user must assume there is not an access in progress.
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The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the SDRAM device at the same time. The arbitration type is round-robin arbitration. This algorithm dispatches the requests from different masters to the SDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is serviced first, then the others are serviced in a round-robin manner.
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30.5.6 Write Protected Registers To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be writeprotected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
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30.6 Software Interface/SDRAM Organization, Address Mapping The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps different memory types depending on the values set in the DDRSDRC Configuration Register. See Section 30.7.3 “DDRSDRC Configuration Register” on page 433. The following figures illustrate the relation between CPU addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths.
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Table 30-4. Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 Bk[1:0] 17 16 15 14 13 12 11 10 9 8 7 Row[13:0] Bk[1:0] 5 4 3 2 1 M0 Column[9:0] Row[13:0] 0 M0 Column[8:0] Row[13:0] Bk[1:0] 6 M0 Column[10:0] Table 30-5.
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Table 30-8. Interleaved Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[13:0] 11 10 9 8 7 Bk[1:0] Row[13:0] 5 4 3 2 1 M0 Column[9:0] Bk[1:0] 0 M0 Column[8:0] Bk[1:0] Row[13:0] 6 M0 Column[10:0] 30.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks Table 30-9.
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Table 30-13. SDR-SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 Bk[1:0] 16 15 14 13 12 11 10 9 8 Row[10:0] Bk[1:0] 6 5 4 3 2 Column[8:0] Row[10:0] Bk[1:0] 7 0 M[1:0] Column[9:0] Row[10:0] 1 M[1:0] Column[10:0] M[1:0] Table 30-14.
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30.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface The User Interface is connected to the APB bus. The DDRSDRC is programmed using the registers listed in Table 30-16 Table 30-16.
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30.7.1 DDRSDRC Mode Register Name: DDRSDRC_MR Address: 0xFFFFE800 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – MODE This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 445.
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30.7.2 DDRSDRC Refresh Timer Register Name: DDRSDRC_RTR Address: 0xFFFFE804 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – 7 6 5 4 1 0 COUNT 3 2 COUNT This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 445.
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30.7.3 DDRSDRC Configuration Register Name: DDRSDRC_CR Address: 0xFFFFE808 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – DECOD – NB – ACTBST – EBISHARE 15 14 13 12 11 10 9 8 – – DIS_DLL DIC/DS 2 1 – 7 OCD 6 5 DLL 4 3 CAS NR 0 NC This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 445.
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CAS DDR2 CAS Latency SDR CAS Latency 011 3 3 100 Reserved Reserved 101 Reserved Reserved 110 Reserved Reserved 111 Reserved Reserved • DLL: Reset DLL Reset value is 0. This field defines the value of Reset DLL. 0 = Disable DLL reset. 1 = Enable DLL reset. This value is used during the power-up sequence. Note: Note: This field is found only in DDR2-SDRAM devices. • DIC/DS: Output Driver Impedance Control Reset value is 0. This field defines the output drive strength.
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• ACTBST: ACTIVE Bank X to Burst Stop Read Access Bank Y Reset value is 0. 0 = After an ACTIVE command in Bank X, BURST STOP command can be issued to another bank to stop current read access. 1 = After an ACTIVE command in Bank X, BURST STOP command cannot be issued to another bank to stop current read access. This field is unique to SDR-SDRAM, Low-power SDR-SDRAM and Low-power DDR1-SDRAM devices. • NB: Number of Banks The reset value is four banks.
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30.7.4 DDRSDRC Timing Parameter 0 Register Name: DDRSDRC_TPR0 Address: 0xFFFFE80C Access: Read-write Reset: See Table 30-16 31 30 29 28 TMRD 23 22 27 26 21 20 19 14 18 13 6 17 16 9 8 1 0 TRP 12 11 10 TRC 7 24 TWTR TRRD 15 25 REDUCE_WRRD TWR 5 TRCD 4 3 2 TRAS This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 445. • TRAS: Active to Precharge Delay Reset Value is 5 cycles.
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• TWTR: Internal Write to Read Delay Reset value is 0. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices. This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 7. • REDUCE_WRRD: Reduce Write to Read Delay Reset value is 0. This field reduces the delay between write to read access for low-power DDR-SDRAM devices with a latency equal to 2. To use this feature, TWTR field must be equal to 0.
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30.7.5 DDRSDRC Timing Parameter 1 Register Name: DDRSDRC_TPR1 Address: 0xFFFFE810 Access: Read-write Reset: See Table 30-16 31 30 29 28 – – – – 23 22 21 20 27 26 25 24 TXP 19 18 17 16 11 10 9 8 2 1 0 TXSRD 15 14 13 12 TXSNR 7 6 5 – – – 4 3 TRFC This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 445. • TRFC: Row Cycle Delay Reset Value is 8 cycles.
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30.7.6 DDRSDRC Timing Parameter 2 Register Name: DDRSDRC_TPR2 Address: 0xFFFFE814 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 9 8 1 0 TFAW 11 10 TRTP 7 6 5 TRPA 4 3 2 TXARDS TXARD This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” on page 445. • TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
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30.7.7 DDRSDRC Low-power Register Name: DDRSDRC_LPR Address: 0xFFFFE81C Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – APDE 15 14 11 10 9 8 – – 7 6 – UPD_MR 13 12 TIMEOUT 5 – 4 PASR 3 DS 2 CLK_FR 1 0 LPCB • LPCB: Low-power Command Bit Reset value is “00”. 00 = Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
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After the initialization sequence, as soon as DS field is modified, Extended Mode Register is accessed automatically and DS bits are updated. In function of UPD_MR bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access. • TIMEOUT: Low Power Mode Reset value is “00”. This field defines when low-power mode is enabled. 00 The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
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30.7.8 DDRSDRC Memory Device Register Name: DDRSDRC_MD Address: 0xFFFFE820 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – DBW – MD This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 445. • MD: Memory Device Indicates the type of memory used.
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30.7.9 DDRSDRC DLL Register Name: DDRSDRC_DLL Address: 0xFFFFE824 Access: Read-only Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 MDVAL 7 6 5 4 3 2 1 0 – – – – – MDOVF MDDEC MDINC The DLL logic is internally used by the controller in order to delay DQS inputs. This is necessary to center the strobe time and the data valid window.
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30.7.10 DDRSDRC High Speed Register Name: DDRSDRC_HS Address: 0xFFFFE82C Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – DIS_ANTICIP_RE AD – – – – – – This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 445.
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30.7.11 DDRSDRC Write Protect Mode Register Name: DDRSDRC_WPMR Address: 0xFFFFE8E4 Access: Read-write Reset See Table 30-16 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
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30.7.12 DDRSDRC Write Protect Status Register Name: DDRSDRC_WPSR Address: 0xFFFFE8E8 Access: Read-only Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DDRSDRC_WPSR register.
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31. DMA Controller (DMAC) 31.1 Description The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer.
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31.3 Block Diagram Figure 31-1.
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31.4 Functional Description 31.4.1 Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
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Figure 31-2. DMAC Transfer Hierarchy for Non-Memory Peripheral DMAC Transfer Buffer Buffer Chunk Transfer AMBA Burst Transfer DMA Transfer Level Buffer Transfer Level Buffer Chunk Transfer Chunk Transfer AMBA Single Transfer AMBA Burst Transfer AMBA Burst Transfer Single Transfer DMA Transaction Level AMBA Single Transfer AMBA Transfer Level Figure 31-3.
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z Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory where the next linked list item (LLI) exists. The LLI is a set of registers that describe the next buffer (buffer descriptor) and a descriptor pointer register. The DMAC fetches the LLI at the beginning of every buffer when buffer chaining is enabled. z Replay – The DMAC automatically reloads the channel registers at the end of each buffers to the value when the channel was first enabled.
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31.4.3 Handshaking Interface Handshaking interfaces are used at the transaction level to control the flow of single or chunk transfers. The operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow controller. The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over the AMBA bus.
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When buffer chaining using linked lists is the multi-buffer method of choice, and on successive buffers, the DMAC_DSCRx register in the DMAC is re-programmed using the following method: z Buffer chaining using linked lists A buffer descriptor (LLI) consists of following registers, DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx, DMAC_CTRLBx.These registers, along with the DMAC_CFGx register, are used by the DMAC to set up and describe the buffer transfer. 31.4.4.
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31.4.4.2 Programming DMAC for Multiple Buffer Transfers Table 31-1.
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Replay Mode of Channel Registers During automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer and the new values used for the new buffer. Depending on the row number in Table 31-1 on page 454, some or all of the DMAC_SADDRx, DMAC_DADDRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their initial value at the start of a buffer transfer.
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5. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers for channel x. For example, in the register, you can program the following: z i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. z ii. Set up the transfer characteristics, such as: z Transfer width for the source in the SRC_WIDTH field.
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3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Note: Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel.
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Figure 31-6. Multi-buffer with Linked List Address for Source and Destination Address of Destination Layer Address of Source Layer Buffer 2 SADDR(2) Buffer 2 DADDR(2) Buffer 1 SADDR(1) Buffer 1 DADDR(1) Buffer 0 Buffer 0 DADDR(0) SADDR(0) Source Buffers Destination Buffers If the user needs to execute a DMAC transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx.
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Figure 31-8.
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Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10) 1. Read the Channel Handler Status register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. Program the following channel registers: 1. Write the starting source address in the DMAC_SADDRx register for channel x. 2.
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6. The DMAC transfer proceeds as follows: 1. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has completed. It then stalls until the STALx bit of DMAC_CHSR register is cleared by software, writing ‘1’ to DMAC_CHER.KEEPx bit, where x is the channel number.
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Figure 31-10.
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4. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel.
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Buffer Transfer Completed Interrupt, or poll for the Channel Enable. (DMAC_CHSR.ENAx) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 31-1 on page 454, the following step is performed. 19. The DMAC fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers.
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Figure 31-12.
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z Incrementing/decrementing or fixed address for source in SRC_INCR field. z Incrementing/decrementing or fixed address for destination in DST_INCR field. 5. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 6. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. 7. Write the channel configuration information into the DMAC_CFGx register for channel x. z i.
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Figure 31-13.
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Figure 31-14.
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3. Note: 4. Write the starting destination address in the DMAC_DADDRx register for channel x. The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory.
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18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, then automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register is left unchanged.
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Figure 31-16.
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31.4.6 Disabling a Channel Prior to Transfer Completion Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler Enable Register, DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx register bit. The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register. 1.
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31.5 DMAC Software Requirements z There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel. z When the destination peripheral has been defined as the flow controller, source single transfer requests are not serviced until the destination peripheral has asserted its Last Transfer Flag.
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31.6 Write Protection Registers To prevent any single software error that may corrupt the DMAC behavior, the DMAC address space can be writeprotected by setting the WPEN bit in the “DMAC Write Protect Mode Register” (DMAC_WPMR). If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the DMAC Write Protect Status Register (MCI_WPSR) is set, and the WPVSRC field indicates in which register the write access has been attempted.
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31.7 DMA Controller (DMAC) User Interface Table 31-2.
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31.7.1 DMAC Global Configuration Register Name: DMAC_GCFG Address: 0xFFFFEC00 (0), 0xFFFFEE00 (1) Access: Read-write Reset: 0x00000010 Note: 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ARB_CFG 3 – 2 – 1 – 0 – Bit fields 0, 1, 2, 3, have a default value of 0. This should not be changed.
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31.7.2 DMAC Enable Register Name: DMAC_EN Address: 0xFFFFEC04 (0), 0xFFFFEE04 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 ENABLE This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” . • ENABLE: General Enable of DMA 0: DMA Controller is disabled. 1: DMA Controller is enabled.
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31.7.3 DMAC Software Single Request Register Name: DMAC_SREQ Address: 0xFFFFEC08 (0), 0xFFFFEE08 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DSREQ7 14 SSREQ7 13 DSREQ6 12 SSREQ6 11 DSREQ5 10 SSREQ5 9 DSREQ4 8 SSREQ4 7 DSREQ3 6 SSREQ3 5 DSREQ2 4 SSREQ2 3 DSREQ1 2 SSREQ1 1 DSREQ0 0 SSREQ0 • DSREQx: Destination Request Request a destination single transfer on channel i.
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31.7.4 DMAC Software Chunk Transfer Request Register Name: DMAC_CREQ Address: 0xFFFFEC0C (0), 0xFFFFEE0C (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DCREQ7 14 SCREQ7 13 DCREQ6 12 SCREQ6 11 DCREQ5 10 SCREQ5 9 DCREQ4 8 SCREQ4 7 DCREQ3 6 SCREQ3 5 DCREQ2 4 SCREQ2 3 DCREQ1 2 SCREQ1 1 DCREQ0 0 SCREQ0 • DCREQx: Destination Chunk Request Request a destination chunk transfer on channel i.
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31.7.
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31.7.
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31.7.
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31.7.
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31.7.
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31.7.10 DMAC Channel Handler Enable Register Name: DMAC_CHER Address: 0xFFFFEC28 (0), 0xFFFFEE28 (1) Access: Write-only Reset: 0x00000000 31 KEEP7 30 KEEP6 29 KEEP5 28 KEEP4 27 KEEP3 26 KEEP2 25 KEEP1 24 KEEP0 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SUSP7 14 SUSP6 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 ENA7 6 ENA6 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 • ENAx: Enable [7:0] When set, a bit of the ENA field enables the relevant channel.
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31.7.11 DMAC Channel Handler Disable Register Name: DMAC_CHDR Address: 0xFFFFEC2C (0), 0xFFFFEE2C (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RES7 14 RES6 13 RES5 12 RES4 11 RES3 10 RES2 9 RES1 8 RES0 7 DIS7 6 DIS6 5 DIS5 4 DIS4 3 DIS3 2 DIS2 1 DIS1 0 DIS0 • DISx: Disable [7:0] Write one to this field to disable the relevant DMAC Channel.
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31.7.
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31.7.13 DMAC Channel x [x = 0..7] Source Address Register Name: DMAC_SADDRx [x = 0..
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31.7.14 DMAC Channel x [x = 0..7] Destination Address Register Name: DMAC_DADDRx [x = 0..
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31.7.15 DMAC Channel x [x = 0..7] Descriptor Address Register Name: DMAC_DSCRx [x = 0..
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31.7.16 DMAC Channel x [x = 0..7] Control A Register Name: DMAC_CTRLAx [x = 0..
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• SRC_WIDTH: Transfer Width for the Source Value Name Description 00 BYTE the transfer size is set to 8-bit width 01 HALF_WORD the transfer size is set to 16-bit width 1X WORD the transfer size is set to 32-bit width • DST_WIDTH: Transfer Width for the Destination Value Name Description 00 BYTE the transfer size is set to 8-bit width 01 HALF_WORD the transfer size is set to 16-bit width 1X WORD the transfer size is set to 32-bit width • DONE: Current Descriptor Stop Command and Trans
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31.7.17 DMAC Channel x [x = 0..7] Control B Register Name: DMAC_CTRLBx [x = 0..
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• DST_DSCR: Destination Address Descriptor 0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination. • FC: Flow Control This field defines which device controls the size of the buffer transfer, also referred to as the Flow Controller.
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31.7.18 DMAC Channel x [x = 0..7] Configuration Register Name: DMAC_CFGx [x = 0..
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• LOCK_IF: Interface Lock 0 (DISABLE): Interface Lock capability is disabled 1 (ENABLE): Interface Lock capability is enabled • LOCK_B: Bus Lock 0 (DISABLE): AHB Bus Locking capability is disabled. 1(ENABLE): AHB Bus Locking capability is enabled. • LOCK_IF_L: Master Interface Arbiter Lock 0 (CHUNK): The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 (BUFFER): The Master Interface Arbiter is locked by the channel x for a buffer transfer.
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31.7.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register Name: DMAC_SPIPx [x = 0..
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31.7.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register Name: DMAC_DPIPx [x = 0..
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31.7.21 DMAC Write Protect Mode Register Name: DMAC_WPMR Address: 0xFFFFEDE4 (0), 0xFFFFEFE4 (1) Access: Read-write Reset: See Table 31-2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII).
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31.7.22 DMAC Write Protect Status Register Name: DMAC_WPSR Address: 0xFFFFEDE8 (0), 0xFFFFEFE8 (1) Access: Read-only Reset: See Table 31-2 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DMAC_WPSR register.
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32. USB High Speed Device Port (UDPHS) 32.1 Description The USB High Speed Device Port (UDPHS) is compliant with the Universal Serial Bus (USB), rev 2.0 High Speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a Dual-port RAM used to store the current data payload.
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32.3 Block Diagram Figure 32-1. Block Diagram APB Interface APB bus ctrl status DHSDP DHSDM AHB1 AHB bus Rd/Wr/Ready DMA AHB0 AHB bus UTMI USB2.
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32.4 Typical Connection Figure 32-2. Board Schematic PIO (VBUS DETECT) 15k Ω (1) "B" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND 1 DHSDM 39 ± 1% Ω DFSDM 2 Shell = Shield (1) 22k Ω CRPB 3 DHSDP 4 39 ± 1% Ω CRPB:1µF to 10µF DFSDP 6K8 ± 1% Ω VBG 10 pF GNDUTMI Note: 32.5 The values shown on the 22 kΩ and 15 kΩ resistors are only valid with 3V3 supplied PIOs. Both 39 Ω resistors need to be placed as close to the device pins as possible. Product Dependencies 32.5.
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32.6 Functional Description 32.6.1 UTMI Transceivers Sharing The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second UTMI transceiver. The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register. Figure 32-3. USB Selection others Transceivers HS Transceiver EN_UDPHS 0 Others Ports 1 PA HS USB Host HS EHCI FS OHCI DMA HS USB Device DMA 32.6.2 USB V2.
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32.6.4 USB Transfer Event Definitions A transfer is composed of one or several transactions; Table 32-3.
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Figure 32-4. Control Read and Write Sequences Setup Stage Control Write Setup TX Data Stage Data OUT TX Setup Stage Control Read No Data Control Setup TX Status Stage Status IN TX Data OUT TX Data Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Status Stage Data IN TX Status OUT TX A status IN or OUT transaction is identical to a data IN or OUT transaction. 32.6.
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The size of the DPRAM is 4 KB. The DPR is shared by all active endpoints. The memory size required by the active endpoints must not exceed the size of the DPRAM. SIZE_DPRAM = SIZE _EPT0 + NB_BANK_EPT1 x SIZE_EPT1 + NB_BANK_EPT2 x SIZE_EPT2 + NB_BANK_EPT3 x SIZE_EPT3 + NB_BANK_EPT4 x SIZE_EPT4 + NB_BANK_EPT5 x SIZE_EPT5 + NB_BANK_EPT6 x SIZE_EPT6 +... (refer to 32.7.
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Configuration examples of UDPHS_EPTCTLx (UDPHS Endpoint Control Disable Register (Isochronous Endpoint)) for Bulk IN endpoint type follow below. z z With DMA z AUTO_VALID: Automatically validate the packet and switch to the next bank. z EPT_ENABL: Enable endpoint. Without DMA: z TXRDY: An interrupt is generated after each transmission. z EPT_ENABL: Enable endpoint. Configuration examples of Bulk OUT endpoint type follow below.
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Figure 32-6. Allocation and Reorganization of the DPRAM Free Memory Free Memory Free Memory EPT5 EPT5 EPT5 Free Memory EPT5 Conflict EPT4 EPT4 EPT4 EPT3 EPT3 (always allocated) EPT4 EPT2 EPT2 EPT2 EPT2 EPT1 EPT1 EPT1 EPT1 EPT0 EPT0 EPT0 Device: Device: EPT4 Lost Memory Device: Endpoint 3 Disabled EPT0 Device: UDPHS_EPTCTLENBx.EPT_ENABL = 1 UDPHS_EPTCTLDIS3.EPT_DISABL = 1 UDPHS_EPTCFG3.BK_NUMBER = 0 UDPHS_EPTCFGx.BK_NUMBER <> 0 Endpoints 0..
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32.6.8 Transfer With DMA USB packets of any length may be transferred when required by the UDPHS Device. These transfers always feature sequential addressing. Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance boost with paged memories.
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for( i=1; i<=((AT91C_BASE_UDPHS->UDPHS_IPFEATURES & AT91C_UDPHS_DMA_CHANNEL_NBR)>>4); i++ ) { // RESET endpoint canal DMA: // DMA stop channel command AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Disable endpoint AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLDIS |= 0XFFFFFFFF; // Reset endpoint config AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLCFG = 0; // Reset DMA channel (Buff count and Control field) AT91C_BASE_UDPHS->UDPHS_DMA[i].
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Figure 32-8. NYET Example with Two Endpoint Banks data 0 ACK t=0 data 1 NYET t = 125 μs Bank 1 E Bank 0 F PING ACK t = 250 μs Bank 1 F Bank 1 F Bank 0 E' Bank 0 E data 0 NYET t = 375 μs Bank 1 F Bank 0 E PING t = 500 μs Bank 1 F Bank 0 F NACK PING t = 625 μs Bank 1 E' Bank 0 F ACK E: empty E': begin to empty F: full Bank 1 E Bank 0 F 32.6.10.3Data IN 32.6.10.
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This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate. A Zero Length Packet can be sent by setting just the TXRDY flag in the UDPHS_EPTSETSTAx register. 32.6.10.6Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to the DPR or from the DPR to the processor memory under the UDPHS control.
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Figure 32-9.
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Figure 32-11.Data IN Followed By Status OUT Transfer at the End of a Control Transfer Device Sends the Last Data Payload to Host USB Bus Packets Token IN Device Sends a Status OUT to Host ACK Data IN Token OUT Data OUT (ZLP) ACK Token OUT ACK Data OUT (ZLP) Interrupt Pending RXRDY (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware TX_COMPLT (UDPHS_EPTSTAx) Set by Hardware Note: Cleared by Firmware A NAK handshake is always generated at the first status stage token. Figure 32-12.
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Figure 32-13.Autovalid with DMA Bank (system) Bank 0 Write Bank 1 write bank 0 write bank 1 bank 0 is full Bank 1 Bank 0 Bank 1 write bank 0 bank 1 is full bank 0 is full Bank 0 IN data 0 Bank (usb) Bank 0 IN data 0 IN data 1 Bank 0 Bank 1 Bank 1 Virtual TXRDY Bank 0 Virtual TXRDY Bank 1 TXRDY (Virtual 0 & Virtual 1) Note: In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing data and to send to DMA. 32.6.
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z If no bank is validated yet, the default DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). Then, no data bank is flushed at microframe end. z If no data bank has been validated at the time when a response should be made for the second transaction of NB_TRANS = 3 transactions microframe, a DATA1 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx).
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Algorithm to Fill Several Packets: z The application enables the interrupts of BUSY_BANK and AUTO_VALID. z When a BUSY_BANK interrupt is received, the application knows that all banks available for the endpoint have been filled. Thus, the application can read all banks available. If the application doesn’t know the size of the receive buffer, instead of using the BUSY_BANK interrupt, the application must use RXRDY_TXKL. 32.6.10.
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Figure 32-15.
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z z If NB_TRANS = 2, the sequence should be either z MData0 z MData0/Data1 If NB_TRANS = 1, the sequence should be z Data0 32.6.10.14Isochronous Endpoint Handling: OUT Example The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the UDPHS_EPTSTAx register in the three bit fields as follows: z TOGGLESQ_STA: PID of the data stored in the current bank z CURBK: Number of the bank currently being accessed by the microcontroller.
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Figure 32-18.Stall Handshake Data IN Transfer USB Bus Packets Token IN Stall PID FRCESTALL Cleared by Firmware Set by Firmware Interrupt Pending STALL_SNT Set by Hardware Cleared by Firmware 32.6.11 Speed Identification The high speed reset is managed by the hardware. At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. At the end of the reset process (full or high), the ENDRESET interrupt is generated.
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Figure 32-19.
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32.6.14 Power Modes 32.6.14.1Controlling Device States A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus Specification, Rev 2.0. Figure 32-20.
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32.6.14.3Entering Attached State When no device is connected, the USB FSDP and FSDM signals are tied to GND by 15 KΩ pull-downs integrated in the hub downstream ports. When a device is attached to an hub downstream port, the device connects a 1.5 KΩ pull-up on FSDP. The USB bus line goes into IDLE state, FSDP is pulled-up by the device 1.5 KΩ resistor to 3.3V and FSDM is pulled-down by the 15 KΩ resistor to GND of the host. After pull-up connection, the device enters the powered state.
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Once the resume is detected on the bus, the signal WAKE_UP in the UDPHS_INTSTA is set. It may generate an interrupt if the corresponding bit in the UDPHS_IEN register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. 32.6.14.9Sending an External Resume In Suspend State it is possible to wake-up the host by sending an external resume. The device waits at least 5 ms after being entered in Suspend State before sending an external resume.
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32.7 USB High Speed Device Port (UDPHS) User Interface Table 32-6.
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32.7.
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(See DETACH description above.
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32.7.2 UDPHS Frame Number Register Name: UDPHS_FNUM Address: 0xF803C004 Access: Read-only 31 FNUM_ERR 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 FRAME_NUMBER 9 8 7 6 5 FRAME_NUMBER 4 3 1 MICRO_FRAME_NUM 0 2 • MICRO_FRAME_NUM: Microframe Number Number of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1 ms). One microframe is received each 125 microseconds (1 ms/8).
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32.7.3 UDPHS Interrupt Enable Register Name: UDPHS_IEN Address: 0xF803C010 Access: Read-write 31 – 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Enable 0 = Disable Suspend Interrupt. 1 = Enable Suspend Interrupt.
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• DMA_x: DMA Channel x Interrupt Enable 0 = Disable the interrupts for this channel. 1 = Enable the interrupts for this channel.
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32.7.4 UDPHS Interrupt Status Register Name: UDPHS_INTSTA Address: 0xF803C014 Access: Read-only 31 – 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 SPEED • SPEED: Speed Status 0 = Reset by hardware when the hardware is in Full Speed mode.
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1 = Set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation. Note: this interrupt is generated even if the device controller clock is disabled.
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32.7.5 UDPHS Clear Interrupt Register Name: UDPHS_CLRINT Address: 0xF803C018 Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Clear 0 = No effect. 1 = Clear the DET_SUSPD bit in UDPHS_INTSTA. • MICRO_SOF: Micro Start Of Frame Interrupt Clear 0 = No effect.
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32.7.6 UDPHS Endpoints Reset Register Name: UDPHS_EPTRST Address: 0xF803C01C Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 EPT_6 5 EPT_5 4 EPT_4 3 EPT_3 2 EPT_2 1 EPT_1 0 EPT_0 • EPT_x: Endpoint x Reset 0 = No effect. 1 = Reset the Endpointx state. Setting this bit clears the Endpoint status UDPHS_EPTSTAx register, except for the TOGGLESQ_STA field.
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32.7.
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Upon command, a port’s transceiver must enter the High Speed receive mode and remain in that mode until the exit action is taken. This enables the testing of output impedance, low level output voltage and loading characteristics. In addition, while in this mode, upstream facing ports (and only upstream facing ports) must respond to any IN token packet with a NAK handshake (only if the packet CRC is determined to be correct) within the normal allowed device response time.
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32.7.8 UDPHS Endpoint Configuration Register Name: UDPHS_EPTCFGx [x=0..
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Endpoint Type Value Name Description 0 CTRL8 Control endpoint 1 ISO Isochronous endpoint 2 BULK Bulk endpoint 3 INT Interrupt endpoint • BK_NUMBER: Number of Banks Set this field according to the endpoint’s number of banks (see Section 32.6.6 ”Endpoint Configuration”).
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32.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLENBx [x=0..
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• TXRDY: TX Packet Ready Interrupt Enable 0 = No effect. 1 = Enable TX Packet Ready/Transaction Error Interrupt. • RX_SETUP: Received SETUP 0 = No effect. 1 = Enable RX_SETUP Interrupt. • STALL_SNT: Stall Sent Interrupt Enable 0 = No effect. 1 = Enable Stall Sent Interrupt. • NAK_IN: NAKIN Interrupt Enable 0 = No effect. 1 = Enable NAKIN Interrupt. • NAK_OUT: NAKOUT Interrupt Enable 0 = No effect. 1 = Enable NAKOUT Interrupt. • BUSY_BANK: Busy Bank Interrupt Enable 0 = No effect.
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32.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints) Name: UDPHS_EPTCTLENBx [x=0..
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• TX_COMPLT: Transmitted IN Data Complete Interrupt Enable 0 = No effect. 1 = Enable Transmitted IN Data Complete Interrupt. • TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Enable 0 = No effect. 1 = Enable TX Packet Ready/Transaction Error Interrupt. • ERR_FL_ISO: Error Flow Interrupt Enable 0 = No effect. 1 = Enable Error Flow ISO Interrupt. • ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enable 0 = No effect. 1 = Enable Error CRC ISO/Error Number of Transaction Interrupt.
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32.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLDISx [x=0..
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• TXRDY: TX Packet Ready Interrupt Disable 0 = No effect. 1 = Disable TX Packet Ready/Transaction Error Interrupt. • RX_SETUP: Received SETUP Interrupt Disable 0 = No effect. 1 = Disable RX_SETUP Interrupt. • STALL_SNT: Stall Sent Interrupt Disable 0 = No effect. 1 = Disable Stall Sent Interrupt. • NAK_IN: NAKIN Interrupt Disable 0 = No effect. 1 = Disable NAKIN Interrupt. • NAK_OUT: NAKOUT Interrupt Disable 0 = No effect. 1 = Disable NAKOUT Interrupt.
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32.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint) Name: UDPHS_EPTCTLDISx [x=0..
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• TX_COMPLT: Transmitted IN Data Complete Interrupt Disable 0 = No effect. 1 = Disable Transmitted IN Data Complete Interrupt. • TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Disable 0 = No effect. 1 = Disable TX Packet Ready/Transaction Error Interrupt. • ERR_FL_ISO: Error Flow Interrupt Disable 0 = No effect. 1 = Disable Error Flow ISO Interrupt. • ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Disable 0 = No effect.
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32.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLx [x=0..
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• NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints) 0 = If cleared, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 = If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. Note: According to the Universal Serial Bus Specification, Rev 2.0 (8.5.1.1 NAK Responses to OUT/DATA During PING Protocol), a NAK response to an HS Bulk OUT transfer is expected to be an unusual occurrence.
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• SHRT_PCKT: Short Packet Interrupt Enabled For OUT endpoints: send an Interrupt when a Short Packet has been received. 0 = Short Packet Interrupt is masked. 1 = Short Packet Interrupt is enabled. For IN endpoints: a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling a BULK or INTERRUPT end of transfer, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set.
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32.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint) Name: UDPHS_EPTCTLx [x=0..
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If the exception raised is not associated to a new system bank packet (ex:ERR_FL_ISO), then the request cancellation may happen at any time and may immediately stop the current DMA transfer. This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate.
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• BUSY_BANK: Busy Bank Interrupt Enabled 0 = BUSY_BANK Interrupt is masked. 1 = BUSY_BANK Interrupt is enabled. For OUT endpoints: An interrupt is sent when all banks are busy. For IN endpoints: An interrupt is sent when all banks are free. • SHRT_PCKT: Short Packet Interrupt Enabled For OUT endpoints: send an Interrupt when a Short Packet has been received. 0 = Short Packet Interrupt is masked. 1 = Short Packet Interrupt is enabled.
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32.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTSETSTAx [x=0..
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32.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint) Name: UDPHS_EPTSETSTAx [x=0..
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32.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCLRSTAx [x=0..
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• NAK_OUT: NAKOUT Clear 0 = No effect. 1 = Clear the NAK_OUT flag of UDPHS_EPTSTAx.
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32.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint) Name: UDPHS_EPTCLRSTAx [x=0..
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32.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTSTAx [x=0..
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• RXRDY_TXKL: Received OUT Data/KILL Bank – Received OUT Data (for OUT endpoint or Control endpoint): This bit is set by hardware after a new packet has been stored in the endpoint FIFO. This bit is cleared by the device firmware after reading the OUT data from the endpoint. For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile.
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• NAK_OUT: NAK OUT This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint). • CURBK_CTLDIR: Current Bank/Control Direction – Current Bank (not relevant for Control endpoint): These bits are set by hardware to indicate the number of the current bank.
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32.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint) Name: UDPHS_EPTSTAx [x=0..
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• RXRDY_TXKL: Received OUT Data/KILL Bank – Received OUT Data (for OUT endpoint or Control endpoint): This bit is set by hardware after a new packet has been stored in the endpoint FIFO. This bit is cleared by the device firmware after reading the OUT data from the endpoint. For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile.
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• ERR_CRC_NTR: CRC ISO Error/Number of Transaction Error – CRC ISO Error (for Isochronous OUT endpoints) (Read-only): This bit is set by hardware if the last received data is corrupted (CRC error on data). This bit is updated by hardware when new data is received (Received OUT Data bit).
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• SHRT_PCKT: Short Packet An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
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32.7.21 UDPHS DMA Channel Transfer Descriptor The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer.
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32.7.22 UDPHS DMA Next Descriptor Address Register Name: UDPHS_DMANXTDSCx [x = 0..5] Address: 0xF803C300 [0], 0xF803C310 [1], 0xF803C320 [2], 0xF803C330 [3], 0xF803C340 [4], 0xF803C350 [5] Access: Read-write 31 30 29 28 27 NXT_DSC_ADD 26 25 24 23 22 21 20 19 NXT_DSC_ADD 18 17 16 15 14 13 12 11 NXT_DSC_ADD 10 9 8 7 6 5 4 3 NXT_DSC_ADD 2 1 0 Note: Channel 0 is not used. • NXT_DSC_ADD: Next Descriptor Address This field points to the next channel descriptor to be processed.
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32.7.23 UDPHS DMA Channel Address Register Name: UDPHS_DMAADDRESSx [x = 0..5] Address: 0xF803C304 [0], 0xF803C314 [1], 0xF803C324 [2], 0xF803C334 [3], 0xF803C344 [4], 0xF803C354 [5] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUFF_ADD 23 22 21 20 BUFF_ADD 15 14 13 12 BUFF_ADD 7 6 5 4 BUFF_ADD Note: Channel 0 is not used. • BUFF_ADD: Buffer Address This field determines the AHB bus starting address of a DMA channel transfer.
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32.7.24 UDPHS DMA Channel Control Register Name: UDPHS_DMACONTROLx [x = 0..5] Address: 0xF803C308 [0], 0xF803C318 [1], 0xF803C328 [2], 0xF803C338 [3], 0xF803C348 [4], 0xF803C358 [5] Access: Read-write 31 30 29 28 27 BUFF_LENGTH 26 25 24 23 22 21 20 19 BUFF_LENGTH 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 BURST_LCK 6 DESC_LD_IT 5 END_BUFFIT 4 END_TR_IT 3 END_B_EN 2 END_TR_EN 1 LDNXT_DSC 0 CHANN_ENB Note: Channel 0 is not used.
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• END_TR_EN: End of Transfer Enable (Control) Used for OUT transfers only. 0 = USB end of transfer is ignored. 1 = UDPHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close the current buffer and the UDPHS_DMASTATUSx register END_TR_ST flag will be raised. This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure.
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32.7.25 UDPHS DMA Channel Status Register Name: UDPHS_DMASTATUSx [x = 0..5] Address: 0xF803C30C [0], 0xF803C31C [1], 0xF803C32C [2], 0xF803C33C [3], 0xF803C34C [4], 0xF803C35C [5] Access: Read-write 31 30 29 28 27 BUFF_COUNT 26 25 24 23 22 21 20 19 BUFF_COUNT 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 DESC_LDST 5 END_BF_ST 4 END_TR_ST 3 – 2 – 1 CHANN_ACT 0 CHANN_ENB Note: Channel 0 is not used.
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• DESC_LDST: Descriptor Loaded Status 0 = Cleared automatically when read by software. 1 = Set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
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33. USB Host High Speed Port (UHPHS) 33.1 Description The USB Host High Speed Port (UHPHS) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as Enhanced HCI protocol (Enhanced Host Controller Interface). 33.2 Embedded Characteristics z z Compliant with Enhanced HCI Rev 1.0 Specification z Compliant with USB V2.0 High-speed z Supports High-speed 480 Mbps Compliant with OpenHCI Rev 1.0 Specification z Compliant with USB V2.
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33.3 Block Diagram Figure 33-1. Block Diagram HCI Slave Block AHB Slave OHCI Registers Root Hub Registers List Processor Block Control Embedded USB v2.
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33.4 Typical Connection Figure 33-2.
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33.5 Product Dependencies 33.5.1 I/O Lines HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High Speed physical transceivers are controlled by the USB host controller. One transceiver is shared with the USB High Speed Device (port A). The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register.
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Figure 33-3. UHP Clock Trees UPLL (480 MHz) 30 MHz AHB EHCI Master Interface UTMI transceiver 30 MHz USB 2.0 EHCI Host Controller Port Router EHCI User Interface UTMI transceiver FS transceiver MCK OHCI Master Interface Root Hub and Host SIE UHP48M UHP12M OHCI User Interface USB 1.1 OHCI Host Controller OHCI clocks 33.5.3 Interrupt The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
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33.6 Functional Description 33.6.1 UTMI transceivers Sharing The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second UTMI transceiver. The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register. Figure 33-4. USB Selection Other Transceivers HS Transceiver EN_UDPHS 0 Other Ports HS USB Host HS EHCI FS OHCI DMA 1 PA HS USB Device DMA 33.6.
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34. High Speed MultiMedia Card Interface (HSMCI) 34.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
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34.2 Embedded Characteristics z Compatible with MultiMedia Card Specification Version 4.3 z Compatible with SD Memory Card Specification Version 2.0 z Compatible with SDIO Specification Version 2.0 z Compatible with CE-ATA Specification 1.
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34.3 Block Diagram Figure 34-1. Block Diagram APB Bridge DMAC APB MCCK(1) MCCDA(1) PMC MCK MCDA0(1) HSMCI Interface PIO MCDA1(1) MCDA2(1) MCDA3(1) Interrupt Control HSMCI Interrupt 34.4 Application Block Diagram Figure 34-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc.
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34.5 Pin Name List Table 34-1. I/O Lines Description for 4-bit Configuration Pin Name(1) Pin Description Type(2) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0 - MCDA3 Data 0..3 of Slot A I/O/PP DAT[0..3] of an MMC DAT[0..3] of an SD Card/SDIO Notes: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. 2.
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34.6.3 Interrupt The HSMCI interface has an interrupt line connected to the interrupt controller. Handling the HSMCI interrupt requires programming the interrupt controller before configuring the HSMCI. Table 34-3. Peripheral IDs 34.7 Instance ID HSMCI0 12 HSMCI1 26 Bus Topology Figure 34-3. High Speed MultiMedia Memory Card Bus Topology 1 2 3 4 5 6 7 9 1011 1213 8 MMC The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface.
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Figure 34-4. MMC Bus Connections (One Slot) HSMCI MCDA0 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 1011 9 1011 9 1011 1213 8 MMC1 Note: 1213 8 MMC2 1213 8 MMC3 When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Figure 34-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 34-5. Table 34-5.
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MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Figure 34-6. SD Card Bus Connections with One Slot Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits.
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The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI Command Register. The HSMCI_CMDR allows a command to be carried out.
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The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the Interrupt Enable Register (HSMCI_IER) allows using an interrupt method. Figure 34-7.
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34.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the DMA Controller. In all cases, the block length (BLKLEN field) must be defined either in the Mode Register HSMCI_MR, or in the Block Register HSMCI_BLKR.
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Figure 34-8.
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34.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit DMAEN in the HSMCI_DMA register enables DMA transfer. The following flowchart (Figure 34-9) shows how to write a single block with or without use of DMA facilities.
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Figure 34-9.
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Figure 34-10.
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34.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller 1. Wait until the current command execution has successfully terminated. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI Configuration Register with block_length value. 4. Program the HSMCI_DMA register with the following fields: 3. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR z OFFSET field with dma_offset.
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34.8.6 READ_SINGLE_BLOCK Operation using DMA Controller 34.8.6.1 Block Length is Multiple of 4 1. Wait until the current command execution has successfully completed. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI Configuration Register with block_length value. 4. Set RDPROOF bit in HSMCI_MR to avoid overflow. 5. Program HSMCI_DMA register with the following fields: 1.
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34.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0) In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to use only WORD AHB access. When the block length is no longer a multiple of 4 this is no longer true. The DMA controller is programmed to copy exactly the block length number of bytes using 2 transfer descriptors. 1. Use the previous step until READ_SINGLE_BLOCK then 2.
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–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). 14. Program LLI_B.DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR –SRC_INCR is set to INCR –FC field is programmed with peripheral to memory flow control mode. –Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0. –DIF and SIF are set with their respective layer ID.
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–Both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled) –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously. 8. Program the DMAC_CFGx register for Channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –SRC_H2SEL is set to true to enable hardware handshaking on the destination.
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–Both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled). –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA Controller is able to prefetch data and write HSMCI simultaneously. 8. Program the LLI(n).DMAC_CFGx register for Channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –DST_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_REP is set to 0.
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–SRC_WIDTH is set to WORD –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length/4. 7. Program LLI_W(n).DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR. –SRC_INCR is set to INCR. –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC). –DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
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–SRC_WIDTH is set to WORD. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is skipped later. 8. Program LLI_W(n).DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR. –SRC_INCR is set to INCR. –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
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–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller 17. Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If LLI_B(n) is the last descriptor, then program LLI_B(n).DMAC_DSCR with 0. 18. Program the DMAC_CTRLBx register for Channel x with 0, its content is updated with the LLI Fetch operation. 19. Program DMAC_DSCRx with the address of LLI_W(0) if block_length is greater than 4 else with address of LLI_B(0). 20.
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–DST_REP is set to zero. Address are contiguous. –SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. 9. Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then LLI_W(n).DMAC_DSCRx points to 0. 10.
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34.9.2 SDIO Interrupts Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO interrupt on each slot can be enabled through the HSMCI Interrupt Enable Register. The SDIO interrupt is sampled regardless of the currently selected slot. 34.
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z Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response. z Issue a software reset to the CE-ATA device using FAST_IO (CMD39). If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if the error recovery procedure does not work as expected or there is another timeout, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets all device states.
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34.12 HSMCI Transfer Done Timings 34.12.1 Definition The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished. 34.12.2 Read Access During a read access, the XFRDONE flag behaves as shown in Figure 34-11. Figure 34-11.XFRDONE During a Read Access CMD line HSMCI read CMD Card response The CMDRDY flag is released 8 tbit after the end of the card response. CMDRDY flag Data Last Block 1st Block Not busy flag XFRDONE flag 34.12.
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34.13 Write Protection Registers To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI address space from address offset 0x000 to 0x00FC can be write-protected by setting the WPEN bit in the “HSMCI Write Protect Mode Register” (HSMCI_WPMR).
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34.14 High Speed MultiMedia Card Interface (HSMCI) User Interface Table 34-8.
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34.14.1 HSMCI Control Register Name: HSMCI_CR Address: 0xF0008000 (0), 0xF000C000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN • MCIEN: Multi-Media Interface Enable 0 = No effect. 1 = Enables the Multi-Media Interface if MCDIS is 0. • MCIDIS: Multi-Media Interface Disable 0 = No effect.
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34.14.2 HSMCI Mode Register Name: HSMCI_MR Address: 0xF0008004 (0), 0xF000C004 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 CLKODD 15 – 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 3 2 1 0 CLKDIV This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 630.
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34.14.3 HSMCI Data Timeout Register Name: HSMCI_DTOR Address: 0xF0008008 (0), 0xF000C008 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 DTOMUL 4 3 2 1 0 DTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 630.
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34.14.4 HSMCI SDCard/SDIO Register Name: HSMCI_SDCR Address: 0xF000800C (0), 0xF000C00C (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 5 – 4 – 3 – 2 – 1 7 SDCBUS 0 SDCSEL This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 630. • SDCSEL: SDCard/SDIO Slot Value Name Description 0 SLOTA Slot A is selected.
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34.14.
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34.14.6 HSMCI Command Register Name: HSMCI_CMDR Address: 0xF0008014 (0), 0xF000C014 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 BOOT_ACK 26 ATACS 25 23 – 22 – 21 20 TRTYP 19 18 TRDIR 17 15 – 14 – 13 – 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 6 5 4 3 2 1 0 7 RSPTYP 24 IOSPCMD 16 TRCMD CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD).
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• OPDCMD: Open Drain Command 0 (PUSHPULL) = Push pull command. 1 (OPENDRAIN) = Open drain command. • MAXLAT: Max Latency for Command to Response 0 (5) = 5-cycle max latency. 1 (64) = 64-cycle max latency. • TRCMD: Transfer Command Value Name Description 0 NO_DATA 1 START_DATA Start data transfer 2 STOP_DATA Stop data transfer 3 – No data transfer Reserved • TRDIR: Transfer Direction 0 (WRITE) = Write. 1 (READ) = Read.
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34.14.7 HSMCI Block Register Name: HSMCI_BLKR Address: 0xF0008018 (0), 0xF000C018 (1) Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer.
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34.14.8 HSMCI Completion Signal Timeout Register Name: HSMCI_CSTOR Address: 0xF000801C (0), 0xF000C01C (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 CSTOMUL 4 3 2 1 0 CSTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 630.
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34.14.9 HSMCI Response Register Name: HSMCI_RSPR Address: 0xF0008020 (0), 0xF000C020 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
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34.14.10 HSMCI Receive Data Register Name: HSMCI_RDR Address: 0xF0008030 (0), 0xF000C030 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data to Read 34.14.
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34.14.12 HSMCI Status Register Name: HSMCI_SR Address: 0xF0008040 (0), 0xF000C040 (1) Access: Read-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 – 14 – 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 – 6 – 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY • CMDRDY: Command Ready 0 = A command is in progress. 1 = The last command has been sent.
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For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block. For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data block. The NOTBUSY flag allows to deal with these different states. 0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response. 1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended.
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• DTOE: Data Time-out Error 0 = No error. 1 = The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the HSMCI_SR register. • CSTOE: Completion Signal Time-out Error 0 = No error. 1 = The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading in the HSMCI_SR register. Cleared by reading in the HSMCI_SR register. • BLKOVRE: DMA Block Overrun Error 0 = No error.
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34.14.
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• FIFOEMPTY: FIFO empty Interrupt enable • XFRDONE: Transfer Done Interrupt enable • ACKRCV: Boot Acknowledge Interrupt Enable • ACKRCVE: Boot Acknowledge Error Interrupt Enable • OVRE: Overrun Interrupt Enable • UNRE: Underrun Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
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34.14.
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• FIFOEMPTY: FIFO empty Interrupt Disable • XFRDONE: Transfer Done Interrupt Disable • ACKRCV: Boot Acknowledge Interrupt Disable • ACKRCVE: Boot Acknowledge Error Interrupt Disable • OVRE: Overrun Interrupt Disable • UNRE: Underrun Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
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34.14.
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• FIFOEMPTY: FIFO Empty Interrupt Mask • XFRDONE: Transfer Done Interrupt Mask • ACKRCV: Boot Operation Acknowledge Received Interrupt Mask • ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask • OVRE: Overrun Interrupt Mask • UNRE: Underrun Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
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34.14.16 HSMCI DMA Configuration Register Name: HSMCI_DMA Address: 0xF0008050 (0), 0xF000C050 (1) Access: Read-write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 ROPT 11 – 10 – 9 – 8 DMAEN 7 – 6 5 CHKSIZE 4 3 – 2 – 1 0 OFFSET This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 630.
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34.14.17 HSMCI Configuration Register Name: HSMCI_CFG Address: 0xF0008054 (0), 0xF000C054 (1) Access: Read-write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LSYNC 11 – 10 – 9 – 8 HSMODE 7 – 6 – 5 – 4 FERRCTRL 3 – 2 – 1 – 0 FIFOMODE This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 630.
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34.14.18 HSMCI Write Protect Mode Register Name: HSMCI_WPMR Address: 0xF00080E4 (0), 0xF000C0E4 (1) Access: Read-write 31 30 29 28 27 WP_KEY (0x4D => “M”) 26 25 24 23 22 21 20 19 WP_KEY (0x43 => C”) 18 17 16 15 14 13 12 11 WP_KEY (0x49 => “I”) 10 9 8 7 6 5 2 1 0 WP_EN 4 3 • WP_EN: Write Protection Enable 0 = Disables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII). 1 = Enables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII).
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34.14.
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34.14.20 HSMCI FIFOx Memory Aperture Name: HSMCI_FIFOx[x=0..
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35. Serial Peripheral Interface (SPI) 35.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
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35.3 Block Diagram Figure 35-1. Block Diagram AHB Matrix DMA Ch. Peripheral Bridge APB SPCK MISO PMC MOSI MCK SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 35.4 Application Block Diagram Figure 35-2.
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35.5 Signal Description Table 35-1. Signal Description Pin Name Pin Description Type Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input 35.6 Product Dependencies 35.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
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35.6.3 Interrupt The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires programming the interrupt controller before configuring the SPI. Table 35-3. Peripheral IDs Instance ID SPI0 13 SPI1 14 35.6.4 Direct Memory Access Controller (DMAC) The SPI interface can be used in conjunction with the DMAC in order to reduce processor overhead. For a full description of the DMAC, refer to the corresponding section in the full datasheet. 35.
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Figure 35-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 35-4.
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35.7.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
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35.7.3.1 Master Mode Block Diagram Figure 35-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
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35.7.3.2 Master Mode Flow Diagram Figure 35-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
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Figure 35-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 35-7.
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Figure 35-8. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 35.7.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. z Fixed Peripheral Select: SPI exchanges data with only one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register).
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35.7.3.7 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one NPCS line driven low at a time.
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give even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals, requiring the chip select line to remain active (low) during a full set of transfers might lead to communication errors. To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another chip select is required.
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35.7.3.10Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO controller).
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Figure 35-11.Slave Mode Functional Block Diagram SPCK NSS SPI Clock SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RDRF OVRES RD MSB Shift Register MISO SPI_TDR TD TDRE 35.7.5 Write Protected Registers To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR).
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35.8 Serial Peripheral Interface (SPI) User Interface Table 35-5.
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35.8.1 SPI Control Register Name: SPI_CR Address: 0xF0000000 (0), 0xF0004000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI.
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35.8.2 SPI Mode Register Name: SPI_MR Address: 0xF0000004 (0), 0xF0004004 (1) Access: Read-write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.
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• PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
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35.8.3 SPI Receive Data Register Name: SPI_RDR Address: 0xF0000008 (0), 0xF0004008 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
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35.8.4 SPI Transmit Data Register Name: SPI_TDR Address: 0xF000000C (0), 0xF000400C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
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35.8.
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35.8.
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35.8.
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35.8.
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35.8.9 SPI Chip Select Register Name: SPI_CSRx[x=0..3] Address: 0xF0000030 (0), 0xF0004030 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT – NCPHA CPOL This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. Note: SPI_CSRx registers must be written even if the user wants to use the defaults.
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Value 8 9 10 11 12 13 14 15 Name 16_BIT – – – – – – – Description 16 bits for transfer Reserved Reserved Reserved Reserved Reserved Reserved Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field.
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35.8.
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35.8.11 SPI Write Protection Status Register Name: SPI_WPSR Address: 0xF00000E8 (0), 0xF00040E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register.
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36. Timer Counter (TC) 36.1 Description The Timer Counter (TC) includes six identical 32-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
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36.
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36.3 Block Diagram Figure 36-1.
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36.4 Pin Name List Table 36-3. TC pin list Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O 36.5 Product Dependencies 36.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 36-4.
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36.6 Functional Description 36.6.1 TC Description The six channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 36-5 on page 676. 36.6.2 32-bit Counter Each channel is organized around a 32-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
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Figure 36-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK0 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 36-3.
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36.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 36-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
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36.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock.
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TIOA TIOB SYNC XC2 XC1 XC0 MTIOA MTIOB 1 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 ABETRG CLKI SWTRG If RA is not loaded or RB is Loaded Edge Detector ETRGEDG MCK Synchronous Edge Detection Edge Detector LDRA S R OVF If RA is Loaded CPCTRG Counter RESET Trig CLK Q LDBSTOP R S CLKEN Edge Detector LDRB Capture Register A Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR Timer/Counter Channel BURST TCCLKS Compare RC = Register C COVFS INT
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36.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
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TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG MCK Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TCCLKS TIOB
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36.6.11.1WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 36-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 36-8. RC Compare cannot be programmed to generate a trigger in this configuration.
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36.6.11.2WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 36-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 36-10.
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36.6.11.3WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 36-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-12.
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36.6.11.4WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 36-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-14.
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36.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
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36.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: 0xF8008000 (0)[0], 0xF8008040 (0)[1], 0xF8008080 (0)[2], 0xF800C000 (1)[0], 0xF800C040 (1)[1], 0xF800C080 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect.
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36.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..
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• ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock.
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36.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..
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• EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event. Value Name Description TIOB Direction 0 TIOB TIOB(1) Input 1 XC0 XC0 Output 2 XC1 XC1 Output 3 XC2 XC2 Output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
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• ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BCPB: RB Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • B
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• BEEVT: External Event Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BSWTRG: Software Trigger Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM9G15 [DATASHEET] 11052D–ATARM–31-Oct-12 683
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36.7.4 TC Counter Value Register Name: TC_CVx [x=0..2] Address: 0xF8008010 (0)[0], 0xF8008050 (0)[1], 0xF8008090 (0)[2], 0xF800C010 (1)[0], 0xF800C050 (1)[1], 0xF800C090 (1)[2] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
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36.7.5 TC Register A Name: TC_RAx [x=0..2] Address: 0xF8008014 (0)[0], 0xF8008054 (0)[1], 0xF8008094 (0)[2], 0xF800C014 (1)[0], 0xF800C054 (1)[1], 0xF800C094 (1)[2] Access: Read-only if WAVE = 0, Read-write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RA 23 22 21 20 RA 15 14 13 12 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real time.
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36.7.6 TC Register B Name: TC_RBx [x=0..2] Address: 0xF8008018 (0)[0], 0xF8008058 (0)[1], 0xF8008098 (0)[2], 0xF800C018 (1)[0], 0xF800C058 (1)[1], 0xF800C098 (1)[2] Access: Read-only if WAVE = 0, Read-write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RB 23 22 21 20 RB 15 14 13 12 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time.
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36.7.7 TC Register C Name: TC_RCx [x=0..2] Address: 0xF800801C (0)[0], 0xF800805C (0)[1], 0xF800809C (0)[2], 0xF800C01C (1)[0], 0xF800C05C (1)[1], 0xF800C09C (1)[2] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time.
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36.7.8 TC Status Register Name: TC_SRx [x=0..
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• CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high.
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36.7.9 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Address: 0xF8008024 (0)[0], 0xF8008064 (0)[1], 0xF80080A4 (0)[2], 0xF800C024 (1)[0], 0xF800C064 (1)[1], 0xF800C0A4 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect.
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36.7.10 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Address: 0xF8008028 (0)[0], 0xF8008068 (0)[1], 0xF80080A8 (0)[2], 0xF800C028 (1)[0], 0xF800C068 (1)[1], 0xF800C0A8 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect.
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36.7.11 TC Interrupt Mask Register Name: TC_IMRx [x=0..
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36.7.12 TC Block Control Register Name: TC_BCR Address: 0xF80080C0 (0), 0xF800C0C0 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
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36.7.
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37. Pulse Width Modulation Controller (PWM) 37.1 Description The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
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37.3 Block Diagram Figure 37-1. Pulse Width Modulation Controller Block Diagram PWM Controller PWMx Period Channel PWMx Update Duty Cycle Clock Selector Comparator PWMx Counter PIO PWM0 Channel Period PWM0 Update Duty Cycle Clock Selector PMC MCK Clock Generator Comparator PWM0 Counter APB Interface Interrupt Controller Interrupt Generator APB 37.4 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 37-1.
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37.5 Product Dependencies 37.5.1 I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs.
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37.6 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. z Clocked by the system clock, MCK, the clock generator module provides 13 clocks. z Each channel can independently choose one of the clock generator outputs. z Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 37.6.1 PWM Clock Generator Figure 37-2.
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After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. 37.6.2 PWM Channel 37.6.2.1 Block Diagram Figure 37-3.
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By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (--------------------------------------------------2*X*CPRD*DIVA -) 2*X*CPRD*DIVB -) or (--------------------------------------------------MCK MCK z The waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
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Figure 37-5.
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37.6.3 PWM Controller Operations 37.6.3.1 Initialization Before enabling the output channel, this channel must have been configured by the software application: z Configuration of the clock generator if DIVA and DIVB are required z Selection of the clock for each channel (CPRE field in the PWM_CMRx register) z Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) z Configuration of the period for each channel (CPRD in the PWM_CPRDx register).
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Figure 37-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level.
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37.7 Pulse Width Modulation Controller (PWM) User Interface Table 37-4.
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37.7.1 PWM Mode Register Name: PWM_MR Address: 0xF8034000 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 PREB 19 18 10 DIVB 15 – 14 – 13 – 12 – 11 7 6 5 4 3 PREA 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor Value Name Description 0 CLK_OFF CLKA, CLKB clock is turned off 1 CLK_DIV1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 – CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
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37.7.2 PWM Enable Register Name: PWM_ENA Address: 0xF8034004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. 37.7.
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37.7.4 PWM Status Register Name: PWM_SR Address: 0xF803400C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
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37.7.5 PWM Interrupt Enable Register Name: PWM_IER Address: 0xF8034010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x.
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37.7.6 PWM Interrupt Disable Register Name: PWM_IDR Address: 0xF8034014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x.
PAGE 710
37.7.7 PWM Interrupt Mask Register Name: PWM_IMR Address: 0xF8034018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled.
PAGE 711
37.7.8 PWM Interrupt Status Register Name: PWM_ISR Address: 0xF803401C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
PAGE 712
37.7.9 PWM Channel Mode Register Name: PWM_CMR[0..
PAGE 713
37.7.10 PWM Channel Duty Cycle Register Name: PWM_CDTY[0..3] Address: 0xF8034204 [0], 0xF8034224 [1], 0xF8034244 [2], 0xF8034264 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
PAGE 714
37.7.11 PWM Channel Period Register Name: PWM_CPRD[0..3] Address: 0xF8034208 [0], 0xF8034228 [1], 0xF8034248 [2], 0xF8034268 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 16 bits (internal channel counter size) are significant.
PAGE 715
37.7.12 PWM Channel Counter Register Name: PWM_CCNT[0..3] Address: 0xF803420C [0], 0xF803422C [1], 0xF803424C [2], 0xF803426C [3] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: • The channel is enabled (writing CHIDx in the PWM_ENA register).
PAGE 716
37.7.13 PWM Channel Update Register Name: PWM_CUPD[0..3] Address: 0xF8034210 [0], 0xF8034230 [1], 0xF8034250 [2], 0xF8034270 [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD CUPD: Channel Update Register This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.
PAGE 717
38. Two-wire Interface (TWI) 38.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
PAGE 718
38.2 Embedded Characteristics z Three TWIs z Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices(1) z One, Two or Three Bytes for Slave Address z Sequential Read-write Operations z Master, Multi-master and Slave Mode Operation z Bit Rate: Up to 400 Kbits z General Call Supported in Slave mode z SMBUS Quick Command Supported in Master Mode z Connection to DMA Controller (DMA) Channel Capabilities optimizes Data Transfers in Master Mode Only Note: 38.3 1.
PAGE 719
38.4 Block Diagram Figure 38-1. Block Diagram APB Bridge TWCK PIO PMC MCK TWD Two-wire Interface TWI TWI Interrupt Interrupt 38.5 Interrupt AIC Controller Application Block Diagram Figure 38-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 38.5.1 I/O Lines Description Table 38-3.
PAGE 720
38.6 Product Dependencies 38.6.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 38-2 on page 719). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines.
PAGE 721
38.7 Functional Description 38.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 38-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 38-3). z A high-to-low transition on the TWD line while TWCK is high defines the START condition.
PAGE 722
38.8 Master Mode 38.8.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 38.8.2 Application Block Diagram Figure 38-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 38.8.
PAGE 723
Figure 38-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) S TWD DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 38-7.
PAGE 724
Figure 38-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 38.8.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device.
PAGE 725
Figure 38-9. Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 38-10.Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read Figure 38-11.
PAGE 726
38.8.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 38.8.6.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
PAGE 727
38.8.6.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2.
PAGE 728
38.8.8 SMBUS Quick Command (Master Mode Only) The TWI interface can perform a Quick Command: 1. Configure the master mode (DADR, CKDIV, etc.). 2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent. 3. Start the transfer by setting the QUICK bit in the TWI_CR. Figure 38-15.SMBUS Quick Command TWD S DADR R/W A P TXCOMP TXRDY Write QUICK command in TWI_CR 38.8.
PAGE 729
Figure 38-16.
PAGE 730
Figure 38-17.
PAGE 731
Figure 38-18.
PAGE 732
Figure 38-19.
PAGE 733
Figure 38-20.
PAGE 734
Figure 38-21.
PAGE 735
38.9 Multi-master Mode 38.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
PAGE 736
Figure 38-22.Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 38-23.
PAGE 737
Figure 38-24.
PAGE 738
38.10 Slave Mode 38.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 38.10.2 Application Block Diagram Figure 38-25.
PAGE 739
38.10.4.2Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 38-27 on page 740. 38.10.4.
PAGE 740
38.10.5.2Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
PAGE 741
38.10.5.4Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
PAGE 742
Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 38-30 on page 742 describes the clock synchronization in Read mode. Figure 38-30.
PAGE 743
38.10.5.5Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 38-31 on page 743 describes the repeated start + reversal from Read to Write mode. Figure 38-31.
PAGE 744
38.10.6 Read Write Flowcharts The flowchart shown in Figure 38-33 on page 744 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 38-33.
PAGE 745
38.11 Write Protection System In order to bring security to the TWI, a write protection system has been implemented. The write protection mode prevents the write of “TWI Clock Waveform Generator Register” and “TWI Slave Mode Register”. When this mode is enabled and one of the protected registers is written, an error is generated in the “TWI Write Protection Status Register” and the register write request is canceled.
PAGE 746
38.12 Two-wire Interface (TWI) User Interface Table 38-6.
PAGE 747
38.12.1 TWI Control Register Name: TWI_CR Address: 0xF8010000 (0), 0xF8014000 (1), 0xF8018000 (2) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
PAGE 748
• SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0 = No effect. 1 = If Master mode is enabled, a SMBUS Quick Command is sent. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset.
PAGE 749
38.12.
PAGE 750
38.12.3 TWI Slave Mode Register Name: TWI_SMR Address: 0xF8010008 (0), 0xF8014008 (1), 0xF8018008 (2) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the “TWI Write Protection Mode Register”.
PAGE 751
38.12.4 TWI Internal Address Register Name: TWI_IADR Address: 0xF801000C (0), 0xF801400C (1), 0xF801800C (2) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
PAGE 752
38.12.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0xF8010010 (0), 0xF8014010 (1), 0xF8018010 (2) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV This register can only be written if the WPEN bit is cleared in the “TWI Write Protection Mode Register”. TWI_CWGR is only used in Master mode.
PAGE 753
38.12.6 TWI Status Register Name: TWI_SR Address: 0xF8010020 (0), 0xF8014020 (1), 0xF8018020 (2) Access: Read-only Reset: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame.
PAGE 754
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 38-26 on page 739, Figure 38-29 on page 741, Figure 38-31 on page 743 and Figure 38-32 on page 743. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
PAGE 755
• ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
PAGE 756
38.12.
PAGE 757
38.12.
PAGE 758
38.12.
PAGE 759
38.12.
PAGE 760
38.12.
PAGE 761
38.12.12 TWI Write Protection Mode Register Name: TWI_WPROT_MODE Address: 0xF80100E4 (0), 0xF80140E4 (1), 0xF80180E4 (2) Access: Read-write 31 30 29 28 27 SECURITY_CODE 26 25 24 23 22 21 20 19 SECURITY_CODE 18 17 16 15 14 13 12 11 SECURITY_CODE 10 9 8 7 – 6 – 5 – 4 – 2 – 1 – 0 WPROT 3 – • SECURITY_CODE: Write protection mode security code This security code is needed to set/reset the WPROT bit value (see Section 38.11 “Write Protection System” for details).
PAGE 762
38.12.13 TWI Write Protection Status Register Name: TWI_WPROT_STATUS Address: 0xF80100E8 (0), 0xF80140E8 (1), 0xF80180E8 (2) Access: Read-only 31 30 29 28 27 WPROTADDR 26 25 24 23 22 21 20 19 WPROTADDR 18 17 16 15 14 13 12 11 WPROTADDR 10 9 8 7 – 6 – 5 – 4 – 2 – 1 – 0 WPROTERR 3 – • WPROTADDR: Write Protection Error Address Indicates the address of the register write request which generated the error. • WPROTERR: Write Protection Error Indicates a write protection error.
PAGE 763
39. Universal Synchronous Asynchronous Receiver Transmitter (USART) 39.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
PAGE 764
39.2 Embedded Characteristics z Programmable Baud Rate Generator z 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications z 1, 1.
PAGE 765
39.3 Block Diagram Figure 39-1. USART Block Diagram (Peripheral) DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS PMC MCK DIV SCK Baud Rate Generator MCK/DIV User Interface SLCK APB Table 39-1.
PAGE 766
39.4 Application Block Diagram Figure 39-2.
PAGE 767
39.5 I/O Lines Description Table 39-2.
PAGE 768
39.6 Product Dependencies 39.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
PAGE 769
39.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. using the USART interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. Table 39-4. Peripheral IDs 39.7 Instance ID USART0 5 USART1 6 USART2 7 USART3 8 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications.
PAGE 770
z z Automatic processing and verification of the “Synch Break” and the “Synch Field” z The “Synch Break” is detected even if it is partially superimposed with a data byte z Automatic Identifier parity calculation/sending and verification z Parity sending and verification can be disabled z Automatic Checksum calculation/sending and verification z Checksum sending and verification can be disabled z Support both “Classic” and “Enhanced” checksum types z Full LIN error checking and reporting z
PAGE 771
39.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
PAGE 772
Baud Rate Calculation Example Table 39-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 39-5. Baud Rate Example (OVER = 0) Source Clock Expected Baud Rate MHz Bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.
PAGE 773
39.7.1.2 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
PAGE 774
39.7.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ------ × f Fi where: z B is the bit rate z Di is the bit-rate adjustment factor z Fi is the clock frequency division factor z f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 39-6. Table 39-6.
PAGE 775
Figure 39-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 39.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR).
PAGE 776
Figure 39-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
PAGE 777
The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character.
PAGE 778
Figure 39-10.Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set.
PAGE 779
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur.
PAGE 780
RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 39-14. The sample pulse rejection mechanism applies. In order to increase the compatibility the RXIDLV bit in the US_MAN register allows to inform the USART block of the Rx line idle state value (Rx line undriven), it can be either level one (pull-up) or level zero (pull-down). By default this bit is set to one (Rx line is at level 1 if undriven). Figure 39-14.
PAGE 781
When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register.
PAGE 782
Figure 39-18.ASK Modulator Output 1 0 0 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 Figure 39-19.FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 39.7.3.6 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock.
PAGE 783
Figure 39-21.Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 39.7.3.8 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 784. Even and odd parity bit generation and error detection are supported.
PAGE 784
Figure 39-22.Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 39.7.3.9 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit to 0 and addresses are transmitted with the parity bit to 1.
PAGE 785
Figure 39-23.Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 39-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 39-10. Maximum Timeguard Length Depending on Baud Rate Baud Rate Bit time Timeguard Bit/sec µs ms 1 200 833 212.50 9 600 104 26.
PAGE 786
value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected.
PAGE 787
Figure 39-25.Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 39.7.3.13Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits to 0.
PAGE 788
Figure 39-26.Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 39.7.3.14Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR.
PAGE 789
Figure 39-28.Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 39.7.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported.
PAGE 790
When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 39-30.T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D2 D1 D4 D3 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 39-31.
PAGE 791
39.7.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). 39.7.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication.
PAGE 792
Figure 39-33 shows an example of character transmission. Figure 39-33.IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 1 0 1 0 0 1 1 0 1 TXD 3 16 Bit Period Bit Period 39.7.5.2 IrDA Baud Rate Table 39-13 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 39-13. IrDA Baud Rate Error Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time 3 686 400 115 200 2 0.
PAGE 793
39.7.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
PAGE 794
Figure 39-36.Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 39.7.7 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.
PAGE 795
Operation in SPI Slave Mode is programmed by writing to 0xF the USART_MODE field in the Mode Register.
PAGE 796
Figure 39-37.SPI Transfer Format (CPHA=1, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 6 5 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master ->RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS Figure 39-38.
PAGE 797
39.7.7.5 Character Transmission The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
PAGE 798
LIN provides cost efficient bus communication where the bandwidth and versatility of CAN are not required. The LIN Mode enables processing LIN frames with a minimum of action from the microprocessor. 39.7.8.1 Modes of Operation The USART can act either as a LIN Master node or as a LIN Slave node.
PAGE 799
Figure 39-39.Header Transmission Baud Rate Clock TXD Break Field 13 dominant bits (at 0) Write US_LINIR US_LINIR Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Stop Start ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit ID TXRDY LINBK in US_CSR LINID in US_CSR Write RSTSTA=1 in US_CR 39.7.8.
PAGE 800
Figure 39-40.Header Reception Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit LINBK LINID US_LINIR Write RSTSTA=1 in US_CR 39.7.8.8 Slave Node Synchronization The synchronization is done only in Slave node configuration. The procedure is based on time measurement between falling edges of the Synch Field.
PAGE 801
Figure 39-42.
PAGE 802
39.7.8.9 Identifier Parity A protected identifier consists of two sub-fields; the identifier and the identifier parity. Bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. The USART interface can generate/check these parity bits, but this feature can also be disabled.
PAGE 803
39.7.8.11Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1).
PAGE 804
If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to TFrame_Maximum. If the Frame Slot Mode is disabled (FSDIS = 1) and a frame transfer has been completed, the TXRDY flag is set again immediately.
PAGE 805
Identifier Parity Error This error is generated in Slave node configuration, if the parity of the identifier is wrong. This error can be generated only if the parity feature is enabled (PARDIS = 0). This error is reported by flag LINIPE in the Channel Status Register (US_CSR). Checksum Error This error is generated in Master of Slave node configuration, if the received checksum is wrong. This flag can be set to “1” only if the checksum feature is enabled (CHKDIS = 0).
PAGE 806
Figure 39-45.Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Checksum Data N TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 39-46.
PAGE 807
Figure 39-47.Master Node Configuration, NACT=IGNORE Frame slot = TFrame_Maximum Frame Break Response space Header Data3 Synch Protected Identifier Interframe space Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR LINTC Slave Node Configuration z Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver. z Write USART_MODE in US_MR to select the LIN mode and the Slave Node configuration.
PAGE 808
Figure 39-48.Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 39-49.Slave Node Configuration, NACT = SUBSCRIBE Break Synch Protected Identifier Data 1 Data N-1 TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 39-50.
PAGE 809
Master Node Configuration The user can choose between two DMAC modes by the PDCM bit in the LIN Mode register (US_LINMR): z PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the DMAC in the Transmit Holding register US_THR (instead of the LIN Mode register US_LINMR). Because the DMAC transfer size is limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS are written.
PAGE 810
Slave Node Configuration In this configuration, the DMAC transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (US_LINIR). The LIN mode must be written by the user in the LIN Mode register (US_LINMR). The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT=SUBSCRIBE). Figure 39-53.
PAGE 811
If RETTO is performed, the counter starts counting down immediately from the value TO. Receiver Time-out programming LIN Specification 2.0 1.3 Baud Rate Time-out period TO 1 000 bit/s 4 000 2 400 bit/s 9 600 9 600 bit/s 38 400 4s 19 200 bit/s 76 800 20 000 bit/s 80 000 - 25 000 Tbits 25 000 39.7.9 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows onboard diagnostics.
PAGE 812
Figure 39-56.Local Loopback Mode Configuration RXD Receiver 1 Transmitter TXD 39.7.9.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 39-57. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 39-57.Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 39.7.
PAGE 813
39.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 39-16.
PAGE 814
39.8.1 USART Control Register Name: US_CR Address: 0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS 18 RTSEN 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, see “USART Control Register (SPI_MODE)” on page 816. • RSTRX: Reset Receiver 0: No effect.
PAGE 815
• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
PAGE 816
39.8.2 USART Control Register (SPI_MODE) Name: US_CR (SPI_MODE) Address: 0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 818. • RSTRX: Reset Receiver 0: No effect.
PAGE 817
• FCS: Force SPI Chip Select – Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): FCS = 0: No effect. FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer). • RCS: Release SPI Chip Select – Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin).
PAGE 818
39.8.3 USART Mode Register Name: US_MR Address: 0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3) Access: Read-write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 – 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 15 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 851.
PAGE 819
• CHRL: Character Length. Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode.
PAGE 820
• CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
PAGE 821
39.8.4 USART Mode Register (SPI_MODE) Name: US_MR (SPI_MODE) Address: 0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 18 – 17 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 7 6 5 4 3 2 1 0 CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 818.
PAGE 822
• CHMODE: Channel Mode Value Name Description 0 NORMAL Normal Mode 1 AUTOMATIC 2 LOCAL_LOOPBACK 3 REMOTE_LOOPBACK Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • CPOL: SPI Clock Polarity – Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF): CPOL = 0: The inactive state value of SPCK is logic level zero.
PAGE 823
39.8.5 USART Interrupt Enable Register Name: US_IER Address: 0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)” on page 824.
PAGE 824
39.8.6 USART Interrupt Enable Register (SPI_MODE) Name: US_IER (SPI_MODE) Address: 0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 818.
PAGE 825
39.8.
PAGE 826
39.8.8 USART Interrupt Disable Register Name: US_IDR Address: 0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” on page 827.
PAGE 827
39.8.9 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Address: 0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 818.
PAGE 828
39.8.
PAGE 829
39.8.11 USART Interrupt Mask Register Name: US_IMR Address: 0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Mask Register (SPI_MODE)” on page 830.
PAGE 830
39.8.12 USART Interrupt Mask Register (SPI_MODE) Name: US_IMR (SPI_MODE) Address: 0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 818.
PAGE 831
39.8.
PAGE 832
39.8.14 USART Channel Status Register Name: US_CSR Address: 0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)” on page 834.
PAGE 833
• TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • ITER: MaxNumber of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. • NACK: Non Acknowledge Interrupt 0: Non Acknowledge has not been detected since the last RSTNACK.
PAGE 834
39.8.15 USART Channel Status Register (SPI_MODE) Name: US_CSR (SPI_MODE) Address: 0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 818.
PAGE 835
39.8.
PAGE 836
• LINBK: LIN Break Sent or LIN Break Received – Applicable if USART operates in LIN Master Mode (USART_MODE = 0xA): 0: No LIN Break has been sent since the last RSTSTA. 1:At least one LIN Break has been sent since the last RSTSTA – If USART operates in LIN Slave Mode (USART_MODE = 0xB): 0: No LIN Break has received sent since the last RSTSTA. 1:At least one LIN Break has been received since the last RSTSTA.
PAGE 837
39.8.17 USART Receive Holding Register Name: US_RHR Address: 0xF801C018 (0), 0xF8020018 (1), 0xF8024018 (2), 0xF8028018 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
PAGE 838
39.8.18 USART Transmit Holding Register Name: US_THR Address: 0xF801C01C (0), 0xF802001C (1), 0xF802401C (2), 0xF802801C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
PAGE 839
39.8.19 USART Baud Rate Generator Register Name: US_BRGR Address: 0xF801C020 (0), 0xF8020020 (1), 0xF8024020 (2), 0xF8028020 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 851.
PAGE 840
39.8.20 USART Receiver Time-out Register Name: US_RTOR Address: 0xF801C024 (0), 0xF8020024 (1), 0xF8024024 (2), 0xF8028024 (3) Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 851. • TO: Time-out Value 0: The Receiver Time-out is disabled.
PAGE 841
39.8.21 USART Transmitter Timeguard Register Name: US_TTGR Address: 0xF801C028 (0), 0xF8020028 (1), 0xF8024028 (2), 0xF8028028 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 851. • TG: Timeguard Value 0: The Transmitter Timeguard is disabled.
PAGE 842
39.8.22 USART FI DI RATIO Register Name: US_FIDI Address: 0xF801C040 (0), 0xF8020040 (1), 0xF8024040 (2), 0xF8028040 (3) Access: Read-write Reset Value: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 851.
PAGE 843
39.8.23 USART Number of Errors Register Name: US_NER Address: 0xF801C044 (0), 0xF8020044 (1), 0xF8024044 (2), 0xF8028044 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE=0x4 or 0x6 in “USART Mode Register” on page 818.
PAGE 844
39.8.24 USART IrDA FILTER Register Name: US_IF Address: 0xF801C04C (0), 0xF802004C (1), 0xF802404C (2), 0xF802804C (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register is relevant only if USART_MODE=0x8 in “USART Mode Register” on page 818.
PAGE 845
39.8.25 USART Manchester Configuration Register Name: US_MAN Address: 0xF801C050 (0), 0xF8020050 (1), 0xF8024050 (2), 0xF8028050 (3) Access: Read-write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 17 16 RX_PL 8 TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 851.
PAGE 846
01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s • RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the US_MAN register.
PAGE 847
39.8.26 USART LIN Mode Register Name: US_LINMR Address: 0xF801C054 (0), 0xF8020054 (1), 0xF8024054 (2), 0xF8028054 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 0 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP NACT This register is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 818.
PAGE 848
• FSDIS: Frame Slot Mode Disable 0: The Frame Slot Mode is enabled. 1: The Frame Slot Mode is disabled. • WKUPTYP: Wakeup Signal Type 0: Setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal. 1: Setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. • DLC: Data Length Control 0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes.
PAGE 849
39.8.27 USART LIN Identifier Register Name: US_LINIR Address: 0xF801C058 (0), 0xF8020058 (1), 0xF8024058 (2), 0xF8028058 (3) Access: Read-write or Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR This register is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 818.
PAGE 850
39.8.28 USART LIN Baud Rate Register Name: US_LINBRR Address: 0xF801C05C (0), 0xF802005C (1), 0xF802405C (2), 0xF802805C (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 LINFP 16 15 14 13 12 11 10 9 8 3 2 1 0 LINCD 7 6 5 4 LINCD This register is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 818. Returns the baud rate value after the synchronization process completion.
PAGE 851
39.8.29 USART Write Protect Mode Register Name: US_WPMR Address: 0xF801C0E4 (0), 0xF80200E4 (1), 0xF80240E4 (2), 0xF80280E4 (3) Access: Read-write Reset: See Table 39-16 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
PAGE 852
39.8.30 USART Write Protect Status Register Name: US_WPSR Address: 0xF801C0E8 (0), 0xF80200E8 (1), 0xF80240E8 (2), 0xF80280E8 (3) Access: Read-only Reset: See Table 39-16 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the US_WPSR register.
PAGE 853
40. Universal Asynchronous Receiver Transmitter (UART) 40.1 Description The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with DMA controller permits packet handling for these tasks with processor time reduced to a minimum. 40.
PAGE 854
40.3 Block Diagram Figure 40-1. UART Functional Block Diagram Peripheral Bridge DMA Controller APB UAR T UTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive URXD Interrupt Control uart_irq Table 40-1.
PAGE 855
40.4 Product Dependencies 40.4.1 I/O Lines The UART pins are multiplexed with PIO lines. The programmer must first configure the corresponding PIO Controller to enable I/O line operations of the UART. Table 40-2. I/O Lines Instance Signal I/O Line Peripheral UART0 URXD0 PC9 C UART0 UTXD0 PC8 C UART1 URXD1 PC17 C UART1 UTXD1 PC16 C 40.4.2 Power Management The UART clock is controllable through the Power Management Controller.
PAGE 856
Figure 40-2. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 40.5.2 Receiver 40.5.2.1 Receiver Reset, Enable and Disable After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register UART_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
PAGE 857
Figure 40-4. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period URXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 40.5.2.3 Receiver Ready When a complete character is received, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is read. Figure 40-5.
PAGE 858
Figure 40-7. Parity Error URXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA 40.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit RSTSTA at 1. Figure 40-8.
PAGE 859
Figure 40-9. Character Transmission Example: Parity enabled Baud Rate Clock UTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 40.5.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register UART_SR. The transmission starts when the programmer writes in the Transmit Holding Register (UART_THR), and after the written character is transferred from UART_THR to the Shift Register.
PAGE 860
Figure 40-11.
PAGE 861
40.6 Universal Asynchronous Receiver Transmitter (UART) User Interface Table 40-3.
PAGE 862
40.6.1 UART Control Register Name: UART_CR Address: 0xF8040000 (0), 0xF8044000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
PAGE 863
40.6.
PAGE 864
40.6.
PAGE 865
40.6.
PAGE 866
40.6.
PAGE 867
40.6.6 UART Status Register Name: UART_SR Address: 0xF8040014 (0), 0xF8044014 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the UART_RHR or the receiver is disabled.
PAGE 868
40.6.7 UART Receiver Holding Register Name: UART_RHR Address: 0xF8040018 (0), 0xF8044018 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
PAGE 869
40.6.8 UART Transmit Holding Register Name: UART_THR Address: 0xF804001C (0), 0xF804401C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
PAGE 870
40.6.
PAGE 871
41. Analog-to-Digital Converter (ADC) 41.1 Description The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the Block Diagram: Figure 41-1. It also integrates a 12-to-1 analog multiplexer, making possible the analog-to-digital conversions of 12 analog lines. The conversions extend from 0V to ADVREF.
PAGE 872
41.
PAGE 873
41.3 Block Diagram Figure 41-1.
PAGE 874
41.5 Product Dependencies 41.5.1 Power Management The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the Power Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled. 41.5.
PAGE 875
41.5.6 Conversion Performances For performance and electrical characteristics of the ADC, see the product DC Characteristics section. 41.6 Functional Description 41.6.1 Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data requires Tracking Clock cycles as defined in the field TRACKTIM of the “ADC Mode Register” on page 895 and Transfer Clock cycles as defined in the field TRANSFER of the same register.
PAGE 876
41.6.2 Conversion Reference The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. 41.6.3 Conversion Resolution The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the LOWRES bit in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used.
PAGE 877
Figure 41-4.
PAGE 878
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the selected signal. Due to asynchronous handling, the delay may vary in a range of 2 MCK clock periods to 1 ADC clock period. trigger start delay Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request.
PAGE 879
41.6.7 Comparison Window The ADC Controller features automatic comparison functions. It compares converted values to a low threshold or a high threshold or both, according to the CMPMODE function chosen in the Extended Mode Register (ADC_EMR). The comparison can be done on all channels or only on the channel specified in CMPSEL field of ADC_EMR. To compare all channels the CMP_ALL parameter of ADC_EMR should be set.
PAGE 880
Figure 41-5. Touchscreen Position Measurement Pen Contact XP YM YP XM VDD XP VDD YP YP XP Volt XM GND Vertical Position Detection Volt YM GND Horizontal Position Detection 41.7.3 4-wire Position Measurement Method As shown in Figure 41-5, to detect the position of a contact, a supply is first applied from top to bottom. Due to the linear resistance of the film, there is a voltage gradient from top to bottom.
PAGE 881
Figure 41-6. Touchscreen Switches Implementation XP VDDANA 0 XM GND 1 To the ADC YP VDDANA 2 YM GND 3 VDDANA VDDANA Switch Resistor Switch Resistor YP XP XP YP YM XM Switch Resistor Switch Resistor GND Horizontal Position Detection GND Vertical Position Detection 41.7.4 4-wire Pressure Measurement Method The method to measure the pressure (Rp) applied to the touchscreen is based on the known resistance of the X-Panel resistance (Rxp).
PAGE 882
Figure 41-7. Pressure Measurement VDDANA VDDANA VDDANA Switch Resistor Switch Resistor XP YP XP YP Rp Open circuit Switch Resistor XP YP Rp YM XM GND XPos Measure(Yp) Rp YM XM YM XM Open circuit Switch Resistor Switch Resistor Open circuit Switch Resistor GND GND Z1 Measure(Xp) Z2 Measure(Xp) 41.7.5 5-wire Resistive Touchscreen Principles To make a 5-wire touchscreen, a resistive layer with a contact point at each corner and a conductive layer are used.
PAGE 883
Figure 41-8. 5-Wire principle UL Pen Contact Resistive layer UR Sense LL LR Conductive Layer UL VDDANA UR VDDANA for Yp GND for Xp Sense LL VDDANA for Xp GND for Yp LR GND 41.7.6 5-wire Position Measurement Method In an application only monitoring clicks, 100 points per second is typically needed. For handwriting or motion detection, the number of measurements to consider is approximately 200 points per second.
PAGE 884
Figure 41-9. Touchscreen Switches Implementation UL VDDANA 0 UR GND VDDANA 1 GND LL VDDANA SENSE LR UL VDDANA 2 To the ADC 3 GND 4 UR VDDANA for Ypos GND for Xpos Sense LL VDDANA for Xpos GND for Ypos LR GND 41.7.7 Sequence and Noise Filtering The ADC Controller can manage ADC conversions and Touchscreen measurement. On each trigger event the sequence of ADC conversions is performed as described in Section 41.6.6 “Sleep Mode and Conversion Sequencer”.
PAGE 885
Figure 41-10.Insertion of Touchscreen sequences (TSFREQ = 2; TSAV = 1) Trigger event ADC_SEL C T C T C C T C C: Classic ADC Conversion Sequence - C T C T: Touch Screen Sequence XRDY Read the ADC_XPOSR Read the ADC_XPOSR YRDY Read the ADC_YPOSR Read the ADC_YPOSR 41.7.8 Measured Values, Registers and Flags As soon as the controller finishes the Touchscreen sequence, XRDY, YRDY and PRDY are set and can generate an interrupt. These flags can be read in the “ADC Interrupt Status Register”.
PAGE 886
Figure 41-11.Touchscreen Pen Detect X+/UL VDDANA 0 X-/UR GND VDDANA 1 GND Y+/LL Y-/SENSE LR VDDANA GND GND 2 To the ADC 3 4 PENDBC Debouncer Pen Interrupt GND The Touchscreen Pen Detect can be used to generate an ADC interrupt to wake up the system. The Pen Detect generates two types of status, reported in the “ADC Interrupt Status Register”: z The PEN bit is set as soon as a contact exceeds the debouncing time as defined by PENDBC and remains set until ADC_SR is read.
PAGE 887
41.7.10 Buffer Structure The DMA read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR) the structure differs.
PAGE 888
When TAG is set (ADC_EMR), the CHNB field (4 most significant bit of the ADC_LCDR) register is set to 0 when XPOS is transmitted and set to 1 when YPOS is transmitted, allowing an easier post-processing of the buffer or better checking buffer integrity. In case 4-wire with pressure mode is selected, Z1 value is transmitted to the buffer along with tag set to 2 and Z2 is tagged with value 3.
PAGE 889
41.7.10.3Interleaved Channels When both classic ADC channels (CH4/CH5 up to CH12 are set in ADC_CHSR) and touchscreen conversions are required (TSMODE differs from 0 in ADC_TSMR register) the structure of the buffer differs according to TSAV and TSFREQ values. If TSFREQ differs from 0, not all events generate touchscreen conversions, therefore buffer structure is based on 2TSFREQ trigger events. Given a TSFREQ value, the location of touchscreen conversion results depends on TSAV value.
PAGE 890
Figure 41-14. Buffer Structure when classic ADC and touchscreen channels are interleaved Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) =1 trig.event1 8 DMA Buffer Structure trig.event2 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) trig.event1 DMA Buffer Structure trig.
PAGE 891
41.7.10.4Pen Detection Status If the pen detection measure is enabled (PENDET is set in ADC_TSMR register), the XPOS, YPOS, Z1, Z2 values transmitted to the buffer through ADC_LCDR register are cleared (including the CHNB field), if the PENS flag of ADC_ISR register is 0. When the PENS flag is set, XPOS, YPOS, Z1, Z2 are normally transmitted.
PAGE 892
41.7.11 Write Protected Registers To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register (ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
PAGE 893
41.8 Analog-to-Digital Converter (ADC) User Interface Any offset not listed in Table 41-4 must be considered as “reserved”. Table 41-4.
PAGE 894
41.8.1 ADC Control Register Name: ADC_CR Address: 0xF804C000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TSCALIB 1 START 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion. • TSCALIB: Touchscreen Calibration 0 = No effect.
PAGE 895
41.8.2 ADC Mode Register Name: ADC_MR Address: 0xF804C004 Access: Read-write 31 USEQ 30 – 29 – 28 – 27 23 – 22 – 21 – 20 – 19 15 14 13 12 26 25 24 17 16 TRACKTIM 18 STARTUP 11 10 9 8 3 2 – 1 0 – PRESCAL 7 – 6 FWUP 5 SLEEP 4 LOWRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 919.
PAGE 896
Value Name Description 5 SUT80 80 periods of ADCClock 6 SUT96 96 periods of ADCClock 7 SUT112 112 periods of ADCClock 8 SUT512 512 periods of ADCClock 9 SUT576 576 periods of ADCClock 10 SUT640 640 periods of ADCClock 11 SUT704 704 periods of ADCClock 12 SUT768 768 periods of ADCClock 13 SUT832 832 periods of ADCClock 14 SUT896 896 periods of ADCClock 15 SUT960 960 periods of ADCClock • TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) * ADCClock periods.
PAGE 897
41.8.3 ADC Channel Sequence 1 Register Name: ADC_SEQR1 Address: 0xF804C008 Access: Read-write 31 30 29 28 27 26 USCH8 23 22 21 20 19 18 USCH6 15 14 13 6 24 17 16 9 8 1 0 USCH5 12 11 10 USCH4 7 25 USCH7 USCH3 5 4 USCH2 3 2 USCH1 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 919.
PAGE 898
41.8.4 ADC Channel Sequence 2 Register Name: ADC_SEQR2 Address: 0xF804C00C Access: Read-write 31 30 29 28 27 26 USCH16 23 22 21 20 19 18 USCH14 15 14 13 6 24 17 16 9 8 1 0 USCH13 12 11 10 USCH12 7 25 USCH15 USCH11 5 4 USCH10 3 2 USCH9 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 919.
PAGE 899
41.8.5 ADC Channel Enable Register Name: ADC_CHER Address: 0xF804C010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 919. • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel.
PAGE 900
41.8.6 ADC Channel Disable Register Name: ADC_CHDR Address: 0xF804C014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 919. • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel.
PAGE 901
41.8.7 ADC Channel Status Register Name: ADC_CHSR Address: 0xF804C018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
PAGE 902
41.8.8 ADC Last Converted Data Register Name: ADC_LCDR Address: 0xF804C020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 0 CHNB 7 6 LDATA 5 4 3 2 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
PAGE 903
41.8.
PAGE 904
41.8.
PAGE 905
41.8.
PAGE 906
41.8.12 ADC Interrupt Status Register Name: ADC_ISR Address: 0xF804C030 Access: Read-only 31 PENS 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished.
PAGE 907
• NOPEN: No Pen contact 0 = No loss of pen contact since the last read of ADC_ISR. 1 = At least one loss of pen contact since the last read of ADC_ISR. • PENS: Pen detect Status 0 = The pen does not press the screen. 1 = The pen presses the screen. Note: PENS is not a source of interruption.
PAGE 908
41.8.13 ADC Overrun Status Register Name: ADC_OVER Address: 0xF804C03C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 • OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_OVER.
PAGE 909
41.8.14 ADC Extended Mode Register Name: ADC_EMR Address: 0xF804C040 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 TAG 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 – 10 – 9 CMPALL 8 – 7 6 4 3 – 2 – 1 0 CMPFILTER 5 CMPSEL CMPMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 919.
PAGE 910
41.8.15 ADC Compare Window Register Name: ADC_CWR Address: 0xF804C044 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 HIGHTHRES 19 18 11 10 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 919. • LOWTHRES: Low Threshold Low threshold associated to compare settings of the ADC_EMR register.
PAGE 911
41.8.16 ADC Channel Data Register Name: ADC_CDRx [x=0..11] Address: 0xF804C050 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
PAGE 912
41.8.17 ADC Analog Control Register Name: ADC_ACR Address: 0xF804C094 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 – 6 – 5 – 4 – 3 – 2 – 1 8 – 0 PENDETSENS This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 919. • PENDETSENS: Pen Detection Sensitivity Allows to modify the pen detection input pull-up resistor value.
PAGE 913
41.8.18 ADC Touchscreen Mode Register Name: ADC_TSMR Address: 0xF804C0B0 Access: Read-write 31 30 29 28 27 – 26 – 18 PENDBC 23 – 22 NOTSDMA 21 – 20 – 19 15 – 14 – 13 – 12 – 11 7 – 6 – 5 4 3 – TSAV 25 – 24 PENDET 17 16 9 8 TSSCTIM 10 TSFREQ 2 – 1 0 TSMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 919.
PAGE 914
• PENDET: Pen Contact Detection Enable 0: Pen contact detection disable. 1: Pen contact detection enable. When PENDET = 1, XPOS, YPOS, Z1, Z2 values of ADC_XPOSR, ADC_YPOSR, ADC_PRESSR registers are automatically cleared when PENS = 0 in ADC_ISR. • NOTSDMA: No TouchScreen DMA 0: XPOS, YPOS, Z1, Z2 are transmitted in ADC_LCDR. 1: XPOS, YPOS, Z1, Z2 are never transmitted in ADC_LCDR, therefore the buffer does not contains touchscreen values.
PAGE 915
41.8.19 ADC Touchscreen X Position Register Name: ADC_XPOSR Address: 0xF804C0B4 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 XSCALE 19 18 11 10 XSCALE 15 – 14 – 13 – 12 – 7 6 5 4 XPOS 3 2 XPOS • XPOS: X Position The Position measured is stored here. if XPOS = 0 or XPOS = XSIZE, the pen is on the border.
PAGE 916
41.8.20 ADC Touchscreen Y Position Register Name: ADC_YPOSR Address: 0xF804C0B8 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 YSCALE 19 18 11 10 YSCALE 15 – 14 – 13 – 12 – 7 6 5 4 YPOS 3 2 YPOS • YPOS: Y Position The Position measured is stored here. if YPOS = 0 or YPOS = YSIZE, the pen is on the border.
PAGE 917
41.8.21 ADC Touchscreen Pressure Register Name: ADC_PRESSR Address: 0xF804C0BC Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 Z2 19 18 11 10 Z2 15 – 14 – 13 – 12 – 7 6 5 4 Z1 3 2 Z1 • Z1: Data of Z1 Measurement Data Z1 necessary to calculate pen pressure. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), Z1 is tied to 0 while there is no detection of contact on the touchscreen (i.e.
PAGE 918
41.8.
PAGE 919
41.8.23 ADC Write Protect Mode Register Name: ADC_WPMR Address: 0xF804C0E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
PAGE 920
41.8.24 ADC Write Protect Status Register Name: ADC_WPSR Address: 0xF804C0E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the ADC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the ADC_WPSR register.
PAGE 921
42. Software Modem Device (SMD) 42.1 Description The Software Modem Device (SMD) is a block for communication via a modem's Digital Isolation Barrier (DIB) with a complementary Line Side Device (HLSD). SMD and HLSD are two parts of the "Transformer only" solution. The transformer is the only component connecting SMD and HLSD. The transformer is used for power, clock and data transfers. Power and clock are supplied by the SMD and consumed by the HLSD. The data flow is bidirectional.
PAGE 922
42.3 Block Diagram Figure 42-1.
PAGE 923
43. Synchronous Serial Controller (SSC) 43.1 Description The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
PAGE 924
43.3 Block Diagram Figure 43-1. Block Diagram System Bus APB Bridge DMA Peripheral Bus TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 43.4 Application Block Diagram Figure 43-2.
PAGE 925
43.5 Pin Name List Table 43-1. I/O Lines Description Pin Name Pin Description RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 43.6 Type Product Dependencies 43.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
PAGE 926
43.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
PAGE 927
43.7.1 Clock Management The transmitter clock can be generated by: z an external clock received on the TK I/O pad z the receiver clock z the internal clock divider The receiver clock can be generated by: z an external clock received on the RK I/O pad z the transmitter clock z the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.
PAGE 928
43.7.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register.
PAGE 929
Figure 43-7. Receiver Clock Management RK (pin) Tri-state Controller MUX Clock Output Transmitter Clock Divider Clock Data Transfer CKO CKS INV MUX Tri-state Controller CKI CKG Receiver Clock 43.7.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers.
PAGE 930
Figure 43-8. Transmitter Block Diagram SSC_CRTXEN TXEN SSC_SRTXEN SSC_CRTXDIS SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_RCMR.START SSC_TCMR.START SSC_TFMR.DATNB SSC_TFMR.DATDEF SSC_TFMR.MSBF RXEN TXEN TX Start TX Start Start RX Start Start RF Selector Selector RF RC0R TX Controller TD Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY != 0 SSC_TFMR.DATLEN 0 SSC_THR Transmitter Clock 1 SSC_TSHR SSC_TFMR.FSLEN TX Controller counter reached STTDLY 43.7.
PAGE 931
Figure 43-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS SSC_TCMR.START SSC_RCMR.START TXEN RX Start RF Start Selector RXEN RF RC0R SSC_RFMR.MSBF SSC_RFMR.DATNB RX Start Start Selector RX Controller RD Receive Shift Register SSC_RCMR.STTDLY != 0 load SSC_RSHR load SSC_RFMR.FSLEN SSC_RHR Receiver Clock SSC_RFMR.DATLEN RX Controller counter reached STTDLY 43.7.
PAGE 932
Figure 43-10.Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF TD (Output) TD (Output) X BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) TD (Output) B1 STTDLY BO X B1 STTDLY TD Start = Level Change on TF (Output) Start = Any Edge on TF BO BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 43-11.
PAGE 933
43.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. z Programmable low or high levels during data transfer are supported. z Programmable high levels before the start of data transfers or toggling are also supported.
PAGE 934
43.7.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: z the event that starts the data transfer (START) z the delay in number of bit periods between the start event and the first data bit (STTDLY) z the length of the data (DATLEN) z the number of data to be transferred for each start event (DATNB).
PAGE 935
Figure 43-14.Transmit Frame Format in Continuous Mode Start Data TD Default Data From SSC_THR From SSC_THR DATLEN DATLEN Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 43-15.Receive Frame Format in Continuous Mode Start = Enable Receiver RD Note: 1.
PAGE 936
Figure 43-16.
PAGE 937
43.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 43-17.Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB MSB Right Channel Left Channel Figure 43-18.
PAGE 938
Figure 43-19.
PAGE 939
43.8.1 Write Protection Registers To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
PAGE 940
43.9 Synchronous Serial Controller (SSC) User Interface Table 43-5.
PAGE 941
43.9.1 SSC Control Register Name: SSC_CR: Address: 0xF0010000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive.
PAGE 942
43.9.2 SSC Clock Mode Register Name: SSC_CMR Address: 0xF0010004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV.
PAGE 943
43.9.3 SSC Receive Clock Mode Register Name: SSC_RCMR Address: 0xF0010010 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 STOP 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
PAGE 944
• CKG: Receive Clock Gating Selection Value Name Description 0 CONTINUOUS None 1 EN_RF_LOW Receive Clock enabled only if RF Pin is Low 2 EN_RF_HIGH Receive Clock enabled only if RF Pin is High • START: Receive Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
PAGE 945
43.9.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0xF0010014 Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 – 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
PAGE 946
• FSOS: Receive Frame Sync Output Selection Value Name Description 0 NONE None, RF pin is an input 1 NEGATIVE Negative Pulse, RF pin is an output 2 POSITIVE Positive Pulse, RF pin is an output 3 LOW Driven Low during data transfer, RF pin is an output 4 HIGH Driven High during data transfer, RF pin is an output 5 TOGGLING Toggling at each start of data transfer, RF pin is an output • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN
PAGE 947
43.9.5 SSC Transmit Clock Mode Register Name: SSC_TCMR Address: 0xF0010018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 – 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
PAGE 948
• START: Transmit Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
PAGE 949
43.9.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0xF001001C Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 FSDEN 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
PAGE 950
Value Name Description 3 LOW TF pin Driven Low during data transfer 4 HIGH TF pin Driven High during data transfer 5 TOGGLING TF pin Toggles at each start of data transfer • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal. 1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
PAGE 951
43.9.7 SSC Receive Holding Register Name: SSC_RHR Address: 0xF0010020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 43.9.
PAGE 952
43.9.9 SSC Receive Synchronization Holding Register Name: SSC_RSHR Address: 0xF0010030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT • RSDAT: Receive Synchronization Data 43.9.
PAGE 953
43.9.11 SSC Receive Compare 0 Register Name: SSC_RC0R Address: 0xF0010038 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • CP0: Receive Compare Data 0 43.9.
PAGE 954
43.9.13 SSC Status Register Name: SSC_SR Address: 0xF0010040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.
PAGE 955
• TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled. • RXEN: Receive Enable 0 = Receive is disabled. 1 = Receive is enabled.
PAGE 956
43.9.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0xF0010044 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt.
PAGE 957
43.9.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0xF0010048 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt.
PAGE 958
43.9.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0xF001004C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.
PAGE 959
43.9.17 SSC Write Protect Mode Register Name: SSC_WPMR Address: 0xF00100E4 Access: Read-write Reset: See Table 43-5 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
PAGE 960
43.9.18 SSC Write Protect Status Register Name: SSC_WPSR Address: 0xF00100E8 Access: Read-only Reset: See Table 43-5 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register.
PAGE 961
44. LCD Controller (LCDC) 44.1 Description The LCD controller consists of logic for transferring LCD image data from an external display buffer to an LCD module. The LCD has one display input buffer per overlay that fetches pixels through the AHB master interface and a lookup table to allow palletized display configurations. The LCD controller is programmable on a per overlay basis, and supports different LCD resolution, window size, image format and pixel depth.
PAGE 962
44.3 Block Diagram Figure 44-1.
PAGE 963
44.4 I/O Lines Description Table 44-1. I/O Lines Description Name Description Type LCD_PWM Contrast control signal, using Pulse Width Modulation Output LCD_HSYNC Horizontal Synchronization Pulse Output LCD_VSYNC Vertical Synchronization Pulse Output LCD_DAT[23:0] LCD 24-bit data bus Output LCD_DEN Data Enable Output LCD_DISP Display Enable signal Output LCD_PCLK Pixel Clock Output 44.5 Product Dependencies 44.5.
PAGE 964
Table 44-2. I/O Lines LCDC LCDDAT20 PC20 A LCDC LCDDAT21 PC21 A LCDC LCDDAT22 PC22 A LCDC LCDDAT23 PC23 A LCDC LCDDEN PC29 A LCDC LCDDISP PC24 A LCDC LCDHSYNC PC28 A LCDC LCDPCK PC30 A LCDC LCDPWM PC26 A LCDC LCDVSYNC PC27 A 44.5.2 Power Management The LCD Controller is not continuously clocked. The user must first enable the LCD Controller clock in the Power Management Controller before using it (PMC_PCER). 44.5.
PAGE 965
44.6 Functional Description The LCD module integrates the following digital blocks: z DMA Engine Address Generation (DEAG). This block performs data prefetch and requests access to the AHB interface. z Input FIFO, stores the stream of pixels. z Color Lookup Table (CLUT). These 256 RAM-based lookup table entries are selected when the color depth is set to 1, 2, 4 or 8 bpp. z Chroma Upsampling Engine (CUE).
PAGE 966
6. Enable the display power signal writing one to the DISPEN field of the LCDC_LCDEN register. 7. Poll DISPSTS field of the LCDC_LCDSR register to check that the power signal is activated. The GUARDTIME field of the LCDC_LCDCFG5 register is used to configure the number of frames before the assertion of the DISP signal. 44.6.1.4 Timing Engine Power Down Software Operation The following sequence is used to disable the display: 1. Disable the DISP signal writing DISPDIS field of the LCDC_LCDDIS register.
PAGE 967
44.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor 1. Write the new descriptor structure in the system memory. 2. Write the address of the new structure in the CHXHEAD register. 3. Add the new structure to the queue of descriptors by writing one to the A2QEN field of the CHXCHER register. 4. The new descriptor will be added to the queue on the next frame. 5. An interrupt will be raised if unmasked, when the head descriptor structure has been loaded by the DMA channel. 44.6.2.
PAGE 968
Table 44-7. DMA address alignment when YUV Mode is selected YUV Mode DMA Address Alignment 32 bpp AYCrCb 32 bit 16 bpp YCrCb 4:2:2 32 bit Y 8 bit 16 bpp semiplanar YCrCb 4:2:2 CrCb 16 bit Y 8 bit 16 bpp planar YCrCb 4:2:2 Cr 8 bit Cb 8 bit Y 8 bit 12 bpp YCrCb 4:2:0 CrCb 16 bit Y 8 bit 12 bpp YCrCb 4:2:0 Cr 8 bit Cb 8 bit 44.6.3 Display Software Configuration 44.6.3.1 System Bus Access Attributes These attributes are defined to improve bandwidth of the pixel stream.
PAGE 969
When the color lookup mode is enabled the following restrictions apply on the horizontal and vertical window size: Table 44-8. Color Lookup Mode and Window Size CLUT Mode x-y Size Requirement 1 bpp multiple of 8 pixels 2 bpp multiple of 4 pixels 4 bpp multiple of 2 pixels 8 bpp free size Pixel striding is disabled when CLUT mode is enabled. When YUV mode is enabled the following restrictions apply on the window size: Table 44-9.
PAGE 970
44.6.4 RGB Frame Buffer Memory Bitmap 44.6.4.1 1 bpp Through Color Lookup Table Table 44-10.
PAGE 971
44.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 Table 44-15. 16 bpp memory mapping, little endian organization Mem addr 0x3 Bit 3 1 Pixel 16 bpp 0x2 3 0 2 9 2 8 2 7 A1[3:0] 2 6 2 5 2 4 2 3 R1[3:0] 0x1 2 2 2 1 2 0 1 9 1 8 G1[3:0] 1 7 1 6 1 5 B1[3:0] 0x0 1 4 1 3 1 2 1 1 A0[3:0] 1 0 9 8 7 6 R0[3:0] 5 4 3 2 G0[3:0] 1 0 B0[3:0] 44.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 Table 44-16.
PAGE 972
44.6.4.1118 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 Table 44-20. 18 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 0x2 Bit 3 1 Pixel 18 bpp G1[1 :0] 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 0x1 2 2 2 1 2 0 1 9 1 8 1 7 1 6 B1[5:0] 1 5 0x0 1 4 1 3 1 2 1 1 1 0 R0[5:0] 9 8 7 6 5 4 G0[5:0] 3 2 1 0 B0[5:0] Table 44-21.
PAGE 973
Table 44-26. 19 bpp packed memory mapping, little endian organization at address 0x8, 0x9, 0xA, 0xB Mem addr 0xB Bit 3 1 Pixel 19 bpp G4[1 :0] 3 0 0xA 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 0x9 2 1 2 0 1 9 1 8 A 3 B4[5:0] 1 7 1 6 1 5 0x8 1 4 1 3 1 2 R3[5:0] 1 1 1 0 9 8 7 6 G3[5:0] 5 4 3 2 1 0 R2[5 :4] B3[3:0] 44.6.4.1424 bpp Unpacked Memory Mapping, RGB 8:8:8 Table 44-27.
PAGE 974
44.6.4.1832 bpp Memory Mapping, RGBA 8:8:8:8 Table 44-32. 32 bpp memory mapping, little endian organization Mem addr 0x3 Bit 3 1 0x2 3 0 2 9 Pixel 32 bpp 2 8 2 7 2 6 2 5 2 4 2 3 0x1 2 2 2 1 R0[7:0] 2 0 1 9 1 8 1 7 1 6 1 5 0x0 1 4 1 3 G0[7:0] 1 2 1 1 1 0 9 8 7 6 5 B0[7:0] 4 3 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 A0[7:0] 44.6.5 YUV Frame Buffer Memory Mapping 44.6.5.1 AYCbCr 4:4:4 Interleaved Frame Buffer Memory Mapping Table 44-33.
PAGE 975
44.6.5.3 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping Table 44-38. 4:2:2 Semiplanar Luminance memory mapping with little endian organization for byte 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 3 1 0x2 3 0 2 9 Pixel 16 bpp 2 8 2 7 2 6 2 5 2 4 2 3 0x1 2 2 2 1 Y3[7:0] 2 0 1 9 1 8 1 7 1 6 1 5 0x0 1 4 1 3 Y2[7:0] 1 2 1 1 1 0 9 8 7 6 5 Y1[7:0] 4 3 2 1 0 2 1 0 2 1 0 1 0 Y0[7:0] Table 44-39.
PAGE 976
Table 44-44. 4:2:0 planar mode Chrominance memory mapping with little endian organization for byte 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 3 1 0x2 3 0 2 9 Pixel 12 bpp 2 8 2 7 2 6 2 5 2 4 2 3 0x1 2 2 2 1 C3[7:0] 2 0 1 9 1 8 1 7 1 6 1 5 0x0 1 4 1 3 C2[7:0] 1 2 1 1 1 0 9 8 7 6 5 C1[7:0] 4 3 2 1 0 2 1 0 2 1 0 2 1 0 C0[7:0] Table 44-45.
PAGE 977
44.6.6 Chrominance Upsampling Unit Both 4:2:2 and 4:2:0 input formats are supported by the LCD module. In 4:2:2, the two chrominance components are sampled at half the sample rate of the luminance. The horizontal chrominance resolution is halved. When this input format is selected, the chrominance upsampling unit uses two chrominances to interpolate the missing component. In 4:2:0, Cr and Cb components are subsampled at a factor of two vertically and horizontally.
PAGE 978
Figure 44-3.
PAGE 979
Figure 44-4.
PAGE 980
Figure 44-5.
PAGE 981
44.6.6.1 Chrominance Upsampling Algorithm 1. Read line n from chrominance cache and interpolate [x/2,0] chrominance component filling the 1 x 2 kernel with line n. If the chrominance cache is empty, then fetch the first line from external memory and interpolate from the external memory. Duplicate the last chrominance at the end of line. 2. Fetch line n+1 from external memory, write line n + 1 to chrominance cache, read line n from the chrominance cache.
PAGE 982
44.6.9.1 Horizontal Scaler The XMEM_SIZE field of the LCDC_HEOCFG4 register indicates the horizontal size minus one of the image in the system memory. The XSIZE field of the LCDC_HEOCFG3 register contains the horizontal size minus one of the window. The SCALEN field of the LCDC_HEOCFG13 register is set to one. The scaling factor is programmed in the XFACTOR field of the LCDC_HEOCFG13 register.
PAGE 983
Figure 44-6.
PAGE 984
44.6.11.2Overlay Blending The blending function requires two pixels (one iterated from the previous blending stage and one from the current overlay color) and a set of blending configuration parameters. These parameters define the color operation. Figure 44-7. Alpha Blender Function iter[n-1] GA OVR From LAEN Shadow REVALPHA Registers ITER ITER2BL CRKEY INV DMA GAEN RGBKEY RGBMASK OVRDEF la ovr blending function iter[n] Figure 44-8.
PAGE 985
44.6.11.3Global Alpha Blender Figure 44-9. Global Alpha Blender base ovr1la ovr1 iter[n-1] la heola heo hcrla hcr ovr blending function iter[n] iter[n-1] la ovr blending function iter[n] iter[n-1] la ovr blending function iter[n] blended pixel 44.6.11.4Window Blending Figure 44-10.
PAGE 986
44.6.11.5Color Keying Color keying involves a method of bit-block image transfer (Blit). This entails blitting one image onto another where not all the pixels are copied. Blitting usually involves two bitmaps, a source bitmap and a destination bitmap. A raster operation (ROP) is performed to define whether the iterated color or the overlay color is to be visible or not. Source Color Keying If the masked overlay color matches the color key then the iterated color is selected.
PAGE 987
44.6.12.2RGB Mode Fetch Performance Table 44-49. RGB Mode Performance Pixels/Cycl e Memory Burst Mode Rotation Optimization(1) Normal Mode 12 bpp 2 1 0.2 Supported 16 bpp 2 1 0.2 Supported 18 bpp 1 1 0.2 Supported 18 bpp RGB PACKED 1.333 Not supported 0.2 Supported 19 bpp 1 1 0.2 Supported 19 bpp PACKED 1.333 Not Supported 0.2 Supported 24 bpp 1 1 0.2 Supported 24 bpp PACKED 1.333 Not Supported 0.2 Supported 25 bpp 1 1 0.2 Supported 32 bpp 1 1 0.
PAGE 988
Table 44-52. YUV Planar Overall Performance 1 AHB Interface For 0 Wait State Memory Pixels/Cycle ROTATION peak random memory access (pixels/cycle) Memory Burst Mode Rotation Optimization Normal Mode 16 bpp 422 semiplanar 2 0.66 0.132 Supported 16 bpp 422 planar 2 0.5 0.1 Supported 12 bpp 4:2:0 semiplanar 2.66 0.8 0.16 Supported 12 bpp 4:2:0 planar 2.66 0.66 0.132 Supported YUV Mode Scaling Burst Mode or Rotation Optimization Available Table 44-53.
PAGE 989
44.6.13 Output Timing Generation 44.6.13.1Active Display Timing Mode Figure 44-11.
PAGE 990
Figure 44-12.
PAGE 991
Figure 44-13.
PAGE 992
Figure 44-14.
PAGE 993
44.6.14 Output Format 44.6.14.1Active Mode Output Pin Assignment Table 44-54.
PAGE 994
44.7 LCD Controller (LCDC) User Interface Table 44-55.
PAGE 995
Table 44-55.
PAGE 996
Table 44-55.
PAGE 997
Table 44-55. Register Mapping (Continued) Offset 0x7FC 0x800 Register Base CLUT Register 255 0xC00-0xFFC 0x1000 Overlay 1 CLUT Register 0 ... (1) Overlay 1 CLUT Register 255 Reserved (1) High End Overlay CLUT Register 0 ... 0x13FC 0x1400 ... High End Overlay CLUT Register 255 0x17FC 0x1800-0x1FE4 Note: (1) (1) Hardware Cursor CLUT Register 0 ... Access Reset LCDC_OVR1CLUT0 Read-write 0x00000000 ... ... ...
PAGE 998
44.7.1 LCD Controller Configuration Register 0 Name: LCDC_LCDCFG0 Address: 0xF8038000 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 – 7 – 14 – 6 – 13 – 5 – 28 – 20 27 – 19 CLKDIV 12 11 CGDISHCR CGDISHEO 4 3 – CLKPWMSEL 26 – 18 25 – 17 24 – 16 10 – 2 CLKSEL 9 CGDISOVR1 1 – 8 CGDISBASE 0 CLKPOL • CLKPOL: LCD Controller Clock Polarity 0: Data/Control signals are launched on the rising edge of the Pixel Clock.
PAGE 999
44.7.2 LCD Controller Configuration Register 1 Name: LCDC_LCDCFG1 Address: 0xF8038004 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 28 – 20 27 – 19 13 – 5 12 – 4 11 – 3 26 – 18 25 – 17 24 – 16 10 – 2 9 – 1 8 – 0 VSPW HSPW • HSPW: Horizontal Synchronization Pulse Width Width of the LCD_HSYNC pulse, given in pixel clock cycles. Width is (HSPW+1) LCD_PCLK cycles.
PAGE 1000
44.7.3 LCD Controller Configuration Register 2 Name: LCDC_LCDCFG2 Address: 0xF8038008 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 28 – 20 27 – 19 13 – 5 12 – 4 11 – 3 26 – 18 25 – 17 24 – 16 10 – 2 9 – 1 8 – 0 VBPW VFPW • VFPW: Vertical Front Porch Width This field indicates the number of lines at the end of the Frame. The blanking interval is equal to (VFPW+1) lines.
PAGE 1001
44.7.4 LCD Controller Configuration Register 3 Name: LCDC_LCDCFG3 Address: 0xF803800C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 14 – 6 13 – 5 12 – 4 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 10 – 2 9 – 1 8 – 0 HBPW HFPW • HFPW: Horizontal Front Porch Width Number of pixel clock cycles inserted at the end of the active line. The interval is equal to (HFPW+1) LCD_PCLK cycles.
PAGE 1002
44.7.5 LCD Controller Configuration Register 4 Name: LCDC_LCDCFG4 Address: 0xF8038010 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 RPF 17 24 9 PPL 1 8 16 RPF 15 – 7 14 – 6 13 – 5 12 – 4 2 0 PPL • RPF: Number of Active Rows Per Frame Number of active lines in the frame. The frame height is equal to (RPF+1) lines. • PPL: Number of Pixels Per Line Number of pixels in the frame.
PAGE 1003
44.7.
PAGE 1004
• MODE: LCD Controller Output Mode Table 44-56. Value Name Description 0 OUTPUT_12BPP LCD output mode is set to 12 bits per pixel 1 OUTPUT_16BPP LCD output mode is set to 16 bits per pixel 2 OUTPUT_18BPP LCD output mode is set to 18 bits per pixel 3 OUTPUT_24BPP LCD output mode is set to 24 bits per pixel • VSPSU: LCD Controller Vertical Synchronization Pulse Setup Configuration 0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge.
PAGE 1005
44.7.7 LCD Controller Configuration Register 6 Name: LCDC_LCDCFG6 Address: 0xF8038018 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 7 – 6 – 5 – 28 – 20 – 12 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 PWMCVAL 4 3 PWMPOL – 2 1 PWMPS 0 • PWMPS: PWM Clock Prescaler 3-bit value. Selects the configuration of the counter prescaler module. The PWMPS field decoding is listed below. Table 44-57.
PAGE 1006
44.7.8 LCD Controller Enable Register Name: LCDC_LCDEN Address: 0xF8038020 Access: Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 PWMEN 26 – 18 – 10 – 2 DISPEN 25 – 17 – 9 – 1 SYNCEN 24 – 16 – 8 – 0 CLKEN • CLKEN: LCD Controller Pixel Clock Enable 0: Writing this field to zero has no effect. 1: When set to one the pixel clock logical unit is activated.
PAGE 1007
44.7.9 LCD Controller Disable Register Name: LCDC_LCDDIS Address: 0xF8038024 Access: Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 PWMRST 3 PWMDIS 26 – 18 – 10 DISPRST 2 DISPDIS 25 – 17 – 9 SYNCRST 1 SYNCDIS 24 – 16 – 8 CLKRST 0 CLKDIS • CLKDIS: LCD Controller Pixel Clock Disable 0: No effect. 1: Disable the pixel clock. • SYNCDIS: LCD Controller Horizontal and Vertical Synchronization Disable 0: No effect.
PAGE 1008
44.7.10 LCD Controller Status Register Name: LCDC_LCDSR Address: 0xF8038028 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 SIPSTS 27 – 19 – 11 – 3 PWMSTS 26 – 18 – 10 – 2 DISPSTS 25 – 17 – 9 – 1 LCDSTS 24 – 16 – 8 – 0 CLKSTS • CLKSTS: Clock Status 0: Pixel Clock is disabled. 1: Pixel Clock is running. • LCDSTS: LCD Controller Synchronization status 0: Timing Engine is disabled. 1: Timing Engine is running.
PAGE 1009
44.7.11 LCD Controller Interrupt Enable Register Name: LCDC_LCDIER Address: 0xF803802C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERRIE 27 – 19 – 11 HCRIE 3 – 26 – 18 – 10 HEOIE 2 DISPIE 25 – 17 – 9 OVR1IE 1 DISIE 24 – 16 – 8 BASEIE 0 SOFIE • SOFIE: Start of Frame Interrupt Enable Register 0: No effect. 1: Enable the interrupt. • DISIE: LCD Disable Interrupt Enable Register 0: No effect. 1: Enable the interrupt.
PAGE 1010
44.7.12 LCD Controller Interrupt Disable Register Name: LCDC_LCDIDR Address: 0xF8038030 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERRID 27 – 19 – 11 HCRID 3 – 26 – 18 – 10 HEOID 2 DISPID 25 – 17 – 9 OVR1ID 1 DISID 24 – 16 – 8 BASEID 0 SOFID • SOFID: Start of Frame Interrupt Disable Register 0: No effect. 1: Disable the interrupt. • DISID: LCD Disable Interrupt Disable Register 0: No effect. 1: Disable the interrupt.
PAGE 1011
44.7.13 LCD Controller Interrupt Mask Register Name: LCDC_LCDIMR Address: 0xF8038034 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERRIM 27 – 19 – 11 HCRIM 3 – 26 – 18 – 10 HEOIM 2 DISPIM 25 – 17 – 9 OVR1IM 1 DISIM 24 – 16 – 8 BASEIM 0 SOFIM • SOFIM: Start of Frame Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled.
PAGE 1012
44.7.14 LCD Controller Interrupt Status Register Name: LCDC_LCDISR Address: 0xF8038038 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERR 27 – 19 – 11 HCR 3 – 26 – 18 – 10 HEO 2 DISP 25 – 17 – 9 OVR1 1 DIS 24 – 16 – 8 BASE 0 SOF • SOF: Start of Frame Interrupt Status Register When set to one, this flag indicates that a start of frame event has been detected. This flag is reset after a read operation.
PAGE 1013
44.7.15 Base Layer Channel Enable Register Name: LCDC_BASECHER Address: 0xF8038040 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enable the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Update windows attributes on the next start of frame.
PAGE 1014
44.7.16 Base Layer Channel Disable Register Name: LCDC_BASECHDR Address: 0xF8038044 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one, this field disables the layer at the end of the current frame. The frame is completed.
PAGE 1015
44.7.17 Base Layer Channel Status Register Name: LCDC_BASECHSR Address: 0xF8038048 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one, this field disables the layer at the end of the current frame.
PAGE 1016
44.7.18 Base Layer Interrupt Enable Register Name: LCDC_BASEIER Address: 0xF803804C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled.
PAGE 1017
44.7.19 Base Layer Interrupt Disable Register Name: LCDC_BASEIDR Address: 0xF8038050 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled.
PAGE 1018
44.7.20 Base Layer Interrupt Mask Register Name: LCDC_BASEIMR Address: 0xF8038054 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled.
PAGE 1019
44.7.21 Base Layer Interrupt Status Register Name: LCDC_BASEISR Address: 0xF8038058 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one, this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
PAGE 1020
44.7.22 Base Layer Head Register Name: LCDC_BASEHEAD Address: 0xF803805C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor.
PAGE 1021
44.7.23 Base Layer Address Register Name: LCDC_BASEADDR Address: 0xF8038060 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer Start Address Frame buffer base address.
PAGE 1022
44.7.24 Base Layer Control Register Name: LCDC_BASECTRL Address: 0xF8038064 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled.
PAGE 1023
44.7.25 Base Layer Next Register Name: LCDC_BASENEXT Address: 0xF8038068 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address DMA Descriptor next address, this address must be word aligned.
PAGE 1024
44.7.26 Base Layer Configuration 0 Register Name: LCDC_BASECFG0 Address: 0xF803806C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 – • BLEN: AHB Burst Length Table 44-58. Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one 32-bit data.
PAGE 1025
44.7.27 Base Layer Configuration 1 Register Name: LCDC_BASECFG1 Address: 0xF8038070 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 7 6 29 – 21 – 13 28 20 – 12 5 4 – RGBMODE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 24 – 16 – 8 CLUTMODE 1 – 0 CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color lookup table is selected. • RGBMODE: RGB Input Mode Selection Table 44-59.
PAGE 1026
44.7.28 Base Layer Configuration 2 Register Name: LCDC_BASECFG2 Address: 0xF8038074 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
PAGE 1027
44.7.29 Base Layer Configuration 3 Register Name: LCDC_BASECFG3 Address: 0xF8038078 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the Base DMA channel is disabled. • GDEF: Green Default Default Green color when the Base DMA channel is disabled. • BDEF: Blue Default Default Blue color when the Base DMA channel is disabled.
PAGE 1028
44.7.30 Base Layer Configuration 4 Register Name: LCDC_BASECFG4 Address: 0xF803807C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 REP 1 – 24 – 16 – 8 DMA 0 – • DMA: Use DMA Data Path 0: The default color is used on the Base Layer. 1: The DMA channel retrieves the pixels stream from the memory.
PAGE 1029
44.7.31 Overlay 1 Layer Channel Enable Register Name: LCDC_OVRCHER1 Address: 0xF8038100 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enable the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Update windows attributes on the next start of frame.
PAGE 1030
44.7.32 Overlay 1 Layer Channel Disable Register Name: LCDC_OVRCHDR1 Address: 0xF8038104 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one, this field disables the layer at the end of the current frame. The frame is completed.
PAGE 1031
44.7.33 Overlay 1 Layer Channel Status Register Name: LCDC_OVRCHSR1 Address: 0xF8038108 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one, this field disables the layer at the end of the current frame.
PAGE 1032
44.7.34 Overlay 1 Layer Interrupt Enable Register Name: LCDC_OVRIER1 Address: 0xF803810C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled.
PAGE 1033
44.7.35 Overlay 1 Layer Interrupt Disable Register Name: LCDC_OVRIDR1 Address: 0xF8038110 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled.
PAGE 1034
44.7.36 Overlay 1 Layer Interrupt Mask Register Name: LCDC_OVRIMR1 Address: 0xF8038114 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled.
PAGE 1035
44.7.37 Overlay 1 Layer Interrupt Status Register Name: LCDC_OVRISR1 Address: 0xF8038118 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
PAGE 1036
44.7.38 Overlay 1 Layer Head Register Name: LCDC_OVRHEAD1 Address: 0xF803811C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor.
PAGE 1037
44.7.39 Overlay 1 Layer Address Register Name: LCDC_OVRADDR1 Address: 0xF8038120 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer Overlay 1 Address Overlay 1 frame buffer base address.
PAGE 1038
44.7.40 Overlay 1 Layer Control Register Name: LCDC_OVRCTRL1 Address: 0xF8038124 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled.
PAGE 1039
44.7.41 Overlay 1 Layer Next Register Name: LCDC_OVRNEXT1 Address: 0xF8038128 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address DMA Descriptor next address, this address must be word aligned.
PAGE 1040
44.7.42 Overlay 1 Layer Configuration 0 Register Name: LCDC_OVR1CFG0 Address: 0xF803812C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 LOCKDIS 5 28 – 20 – 12 ROTDIS 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 – • BLEN: AHB Burst Length Table 44-61. Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one 32-bit data.
PAGE 1041
44.7.43 Overlay 1 Layer Configuration 1 Register Name: LCDC_OVR1CFG1 Address: 0xF8038130 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RGBMODE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 24 – 16 – 8 CLUTMODE 1 – 0 CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color lookup table is selected. • RGBMODE: RGB Input Mode Selection Table 44-62.
PAGE 1042
44.7.44 Overlay 1 Layer Configuration 2 Register Name: LCDC_OVR1CFG2 Address: 0xF8038134 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XPOS • XPOS: Horizontal Window Position Overlay 1 Horizontal window position. • YPOS: Vertical Window Position Overlay 1 Vertical window position.
PAGE 1043
44.7.45 Overlay 1 Layer Configuration 3 Register Name: LCDC_OVR1CFG3 Address: 0xF8038138 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XSIZE • XSIZE: Horizontal Window Size Overlay 1 window width in pixels. The window width is set to (XSIZE+1). The following constraint must be met: XPOS + XSIZE ≤ PPL • YSIZE: Vertical Window Size Overlay 1 window height in pixels.
PAGE 1044
44.7.46 Overlay 1 Layer Configuration 4 Register Name: LCDC_OVR1CFG4 Address: 0xF803813C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
PAGE 1045
44.7.47 Overlay 1 Layer Configuration 5 Register Name: LCDC_OVR1CFG5 Address: 0xF8038140 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PSTRIDE PSTRIDE 15 14 13 12 7 6 5 4 PSTRIDE PSTRIDE • PSTRIDE: Pixel Stride PSTRIDE represents the memory offset, in bytes, between two pixels of the image.
PAGE 1046
44.7.48 Overlay 1 Layer Configuration 6 Register Name: LCDC_OVR1CFG6 Address: 0xF8038144 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the Overlay 1 DMA channel is disabled. • GDEF: Green Default Default Green color when the Overlay 1 DMA channel is disabled.
PAGE 1047
44.7.49 Overlay 1 Layer Configuration 7 Register Name: LCDC_OVR1CFG7 Address: 0xF8038148 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY • RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay.
PAGE 1048
44.7.50 Overlay 1 Layer Configuration 8 Register Name: LCDC_OVR1CFG8 Address: 0xF803814C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK • RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared.
PAGE 1049
44.7.51 Overlay1 Layer Configuration 9 Register Name: LCDC_OVR1CFG9 Address: 0xF8038150 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 OVR 14 – 6 LAEN 13 – 5 GAEN 12 – 4 REVALPHA 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA • CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled.
PAGE 1050
• DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. • REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp, the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp, the pixel is shifted and the least significant bit replicates the MSB.
PAGE 1051
44.7.52 High End Overlay Layer Channel Enable Register Name: LCDC_HEOCHER Address: 0xF8038280 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enable the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Update windows attributes on the next start of frame.
PAGE 1052
44.7.53 High End Overlay Layer Channel Disable Register Name: LCDC_HEOCHDR Address: 0xF8038284 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one, this field disables the layer at the end of the current frame. The frame is completed.
PAGE 1053
44.7.54 High End Overlay Layer Channel Status Register Name: LCDC_HEOCHSR Address: 0xF8038288 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one, this bit indicates that the channel is enabled.
PAGE 1054
44.7.55 High End Overlay Layer Interrupt Enable Register Name: LCDC_HEOIER Address: 0xF803828C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 VOVR 14 UOVR 6 OVR 29 – 21 VDONE 13 UDONE 5 DONE 28 – 20 VADD 12 UADD 4 ADD 27 – 19 VDSCR 11 UDSCR 3 DSCR 26 – 18 VDMA 10 UDMA 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect.
PAGE 1055
• UDONE: End of List for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • UOVR: Overflow for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • VDMA: End of DMA for V Chrominance Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • VDSCR: Descriptor Loaded for V Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled.
PAGE 1056
44.7.56 High End Overlay Layer Interrupt Disable Register Name: LCDC_HEOIDR Address: 0xF8038290 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 VOVR 14 UOVR 6 OVR 29 – 21 VDONE 13 UDONE 5 DONE 28 – 20 VADD 12 UADD 4 ADD 27 – 19 VDSCR 11 UDSCR 3 DSCR 26 – 18 VDMA 10 UDMA 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled.
PAGE 1057
• UDONE: End of List Interrupt for U or UV Chrominance Component Disable Register 0: No effect. 1: Interrupt source is disabled. • UOVR: Overflow Interrupt for U or UV Chrominance Component Disable Register 0: No effect. 1: Interrupt source is disabled. • VDMA: End of DMA Transfer for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • VDSCR: Descriptor Loaded for V Chrominance Component Interrupt Disable Register 0: No effect.
PAGE 1058
44.7.57 High End Overlay Layer Interrupt Mask Register Name: LCDC_HEOIMR Address: 0xF8038294 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 VOVR 14 UOVR 6 OVR 29 – 21 VDONE 13 UDONE 5 DONE 28 – 20 VADD 12 UADD 4 ADD 27 – 19 VDSCR 11 UDSCR 3 DSCR 26 – 18 VDMA 10 UDMA 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled.
PAGE 1059
• UDONE: End of List for U or UV Chrominance Component Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • UOVR: Overflow for U Chrominance Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • VDMA: End of DMA Transfer for V Chrominance Component Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled.
PAGE 1060
44.7.58 High End Overlay Layer Interrupt Status Register Name: LCDC_HEOISR Address: 0xF8038298 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 VOVR 14 UOVR 6 OVR 29 – 21 VDONE 13 UDONE 5 DONE 28 – 20 VADD 12 UADD 4 ADD 27 – 19 VDSCR 11 UDSCR 3 DSCR 26 – 18 VDMA 10 UDMA 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one, this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
PAGE 1061
• VDSCR: DMA Descriptor Loaded for V Component When set to one, this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. • VADD: Head Descriptor Loaded for V Component When set to one, this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. • VDONE: End of List Detected for V Component When set to one, this flag indicates that an End of List condition has occurred.
PAGE 1062
44.7.59 High End Overlay Layer Head Register Name: LCDC_HEOHEAD Address: 0xF803829C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor.
PAGE 1063
44.7.60 High End Overlay Layer Address Register Name: LCDC_HEOADDR Address: 0xF80382A0 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer start Address Frame Buffer Base Address.
PAGE 1064
44.7.61 High End Overlay Layer Control Register Name: LCDC_HEOCTRL Address: 0xF80382A4 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled.
PAGE 1065
44.7.62 High End Overlay Layer Next Register Name: LCDC_HEONEXT Address: 0xF80382A8 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address DMA Descriptor next address, this address must be word aligned.
PAGE 1066
44.7.63 High End Overlay Layer U-UV Head Register Name: LCDC_HEOUHEAD Address: 0xF80382AC Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UHEAD UHEAD 15 14 13 12 7 6 5 4 UHEAD UHEAD • UHEAD: DMA Head Pointer The Head Pointer points to a new descriptor.
PAGE 1067
44.7.64 High End Overlay Layer U-UV Address Register Name: LCDC_HEOUADDR Address: 0xF80382B0 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UADDR UADDR 15 14 13 12 7 6 5 4 UADDR UADDR • UADDR: DMA Transfer Start Address for U or UV Chrominance U or UV frame buffer address.
PAGE 1068
44.7.65 High End Overlay Layer U-UV Control Register Name: LCDC_HEOUCTRL Address: 0xF80382B4 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 UDONEIEN 28 – 20 – 12 – 4 UADDIEN 27 – 19 – 11 – 3 UDSCRIEN 26 – 18 – 10 – 2 UDMAIEN 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 UDFETCH • UDFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled.
PAGE 1069
44.7.66 High End Overlay Layer U-UV Next Register Name: LCDC_HEOUNEXT Address: 0xF80382B8 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UNEXT UNEXT 15 14 13 12 7 6 5 4 UNEXT UNEXT • UNEXT: DMA Descriptor Next Address DMA Descriptor next address, this address must be word aligned.
PAGE 1070
44.7.67 High End Overlay Layer V Head Register Name: LCDC_HEOVHEAD Address: 0xF80382BC Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VHEAD VHEAD 15 14 13 12 7 6 5 4 VHEAD VHEAD • VHEAD: DMA Head Pointer The Head Pointer points to a new descriptor.
PAGE 1071
44.7.68 High End Overlay Layer V Address Register Name: LCDC_HEOVADDR Address: 0xF80382C0 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VADDR VADDR 15 14 13 12 7 6 5 4 VADDR VADDR • VADDR: DMA Transfer Start Address for V Chrominance Frame Buffer Base Address.
PAGE 1072
44.7.69 High End Overlay Layer V Control Register Name: LCDC_HEOVCTRL Address: 0xF80382C4 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 VDONEIEN 28 – 20 – 12 – 4 VADDIEN 27 – 19 – 11 – 3 VDSCRIEN 26 – 18 – 10 – 2 VDMAIEN 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 VDFETCH • VDFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled.
PAGE 1073
44.7.70 High End Overlay Layer V Next Register Name: LCDC_HEOVNEXT Address: 0xF80382C8 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VNEXT VNEXT 15 14 13 12 7 6 5 4 VNEXT VNEXT • VNEXT: DMA Descriptor Next Address Frame Buffer Base Address.
PAGE 1074
44.7.71 High End Overlay Layer Configuration 0 Register Name: LCDC_HEOCFG0 Address: 0xF80382CC Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 LOCKDIS 5 BLENUV 28 – 20 – 12 ROTDIS 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 – • BLEN: AHB Burst Length Table 44-64.
PAGE 1075
• ROTDIS: Hardware Rotation Optimization Disable 0: Rotation optimization is enabled. 1: Rotation optimization is disabled. • LOCKDIS: Hardware Rotation Lock Disable 0: AHB lock signal is asserted when a rotation is performed. 1: AHB lock signal is cleared when a rotation is performed.
PAGE 1076
44.7.72 High End Overlay Layer Configuration 1 Register Name: LCDC_HEOCFG1 Address: 0xF80382D0 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 7 6 29 – 21 – 13 28 – 20 – 12 5 4 YUVMODE RGBMODE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 24 – – 17 16 YUV422SWP YUV422ROT 9 8 CLUTMODE 1 0 YUVEN CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color Lookup table is selected.
PAGE 1077
• CLUTMODE: Color Lookup table input mode selection Table 44-67. Value Name Description 0 1BPP color lookup table mode set to 1 bit per pixel 1 2BPP color lookup table mode set to 2 bits per pixel 2 4BPP color lookup table mode set to 4 bits per pixel 3 8BPP color lookup table mode set to 8 bits per pixel • YUVMODE: YUV input mode selection Table 44-68.
PAGE 1078
44.7.73 High End Overlay Layer Configuration 2 Register Name: LCDC_HEOCFG2 Address: 0xF80382D4 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XPOS • XPOS: Horizontal Window Position High End Overlay Horizontal window position. • YPOS: Vertical Window Position High End Overlay Vertical window position.
PAGE 1079
44.7.74 High End Overlay Layer Configuration 3 Register Name: LCDC_HEOCFG3 Address: 0xF80382D8 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XSIZE • XSIZE: Horizontal Window Size High End Overlay window width in pixels. The window width is set to (XSIZE+1).
PAGE 1080
44.7.75 High End Overlay Layer Configuration 4 Register Name: LCDC_HEOCFG4 Address: 0xF80382DC Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YMEM_SIZE 17 24 9 XMEM_SIZE 1 8 16 YMEM_SIZE 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XMEM_SIZE • XMEM_SIZE: Horizontal image Size in Memory High End Overlay image width in pixels. The image width is set to (XMEM_SIZE+1).
PAGE 1081
44.7.76 High End Overlay Layer Configuration 5 Register Name: LCDC_HEOCFG5 Address: 0xF80382E0 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
PAGE 1082
44.7.77 High End Overlay Layer Configuration 6 Register Name: LCDC_HEOCFG6 Address: 0xF80382E4 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PSTRIDE PSTRIDE 15 14 13 12 7 6 5 4 PSTRIDE PSTRIDE • PSTRIDE: Pixel Stride PSTRIDE represents the memory offset, in bytes, between two pixels of the image memory.
PAGE 1083
44.7.78 High End Overlay Layer Configuration 7 Register Name: LCDC_HEOCFG7 Address: 0xF80382E8 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UVXSTRIDE UVXSTRIDE 15 14 13 12 7 6 5 4 UVXSTRIDE UVXSTRIDE • UVXSTRIDE: UV Horizontal Stride UVXSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
PAGE 1084
44.7.79 High End Overlay Layer Configuration 8 Register Name: LCDC_HEOCFG8 Address: 0xF80382EC Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UVPSTRIDE UVPSTRIDE 15 14 13 12 7 6 5 4 UVPSTRIDE UVPSTRIDE • UVPSTRIDE: UV Pixel Stride UVPSTRIDE represents the memory offset, in bytes, between two pixels of the image memory.
PAGE 1085
44.7.80 High End Overlay Layer Configuration 9 Register Name: LCDC_HEOCFG9 Address: 0xF80382F0 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the High End Overlay DMA channel is disabled. • GDEF: Green Default Default Green color when the High End Overlay DMA channel is disabled.
PAGE 1086
44.7.81 High End Overlay Layer Configuration 10 Register Name: LCDC_HEOCFG10 Address: 0xF80382F4 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY • RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay.
PAGE 1087
44.7.82 High End Overlay Layer Configuration 11 Register Name: LCDC_HEOCFG11 Address: 0xF80382F8 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK • RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared.
PAGE 1088
44.7.83 High End Overlay Layer Configuration 12 Register Name: LCDC_HEOCFG12 Address: 0xF80382FC Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 OVR 14 – 6 LAEN 13 – 5 GAEN 12 VIDPRI 4 REVALPHA 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA • CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled.
PAGE 1089
• DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. • REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the MSB.
PAGE 1090
44.7.84 High End Overlay Layer Configuration 13 Register Name: LCDC_HEOCFG13 Address: 0xF8038300 Access: Read-write Reset: 0x00000000 31 SCALEN 23 30 – 22 29 – 21 28 27 20 19 26 YFACTOR 18 25 24 17 16 10 XFACTOR 2 9 8 1 0 YFACTOR 15 – 7 14 – 6 13 – 5 12 11 4 3 XFACTOR • SCALEN: Hardware Scaler Enable 0: Scaler is disabled 1: Scaler is enabled. • YFACTOR: Vertical Scaling Factor Scaler Vertical Factor. • XFACTOR: Horizontal Scaling Factor Scaler Horizontal Factor.
PAGE 1091
44.7.85 High End Overlay Layer Configuration 14 Register Name: LCDC_HEOCFG14 Address: 0xF8038304 Access: Read-write Reset: 0x00000000 31 – 23 15 30 CSCYOFF 22 CSCRV 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCRV 18 CSCRU 13 12 11 10 9 4 3 2 1 CSCRU 7 6 5 CSCRY 0 CSCRY • CSCRY: Color Space Conversion Y coefficient for Red Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
PAGE 1092
44.7.86 High End Overlay Layer Configuration 15 Register Name: LCDC_HEOCFG15 Address: 0xF8038308 Access: Read-write Reset: 0x00000000 31 – 23 15 30 CSCUOFF 22 CSCGV 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCGV 18 CSCGU 13 12 11 10 9 4 3 2 1 CSCGU 7 6 5 CSCGY 0 CSCGY • CSCGY: Color Space Conversion Y Coefficient for Green Component 1:2:7 Format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
PAGE 1093
44.7.87 High End Overlay Layer Configuration 16 Register Name: LCDC_HEOCFG16 Address: 0xF803830C Access: Read-write Reset: 0x00000000 31 – 23 15 30 CSCVOFF 22 CSCBV 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCBV 18 CSCBU 13 12 11 10 9 4 3 2 1 CSCBU 7 6 5 CSCBY 0 CSCBY • CSCBY: Color Space Conversion Y Coefficient for Blue Component 1:2:7 Format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
PAGE 1094
44.7.88 Hardware Cursor Layer Channel Enable Register Name: LCDC_HCRCHER Address: 0xF8038340 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enable the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Update windows attributes on the next start of frame.
PAGE 1095
44.7.89 Hardware Cursor Layer Channel Disable Register Name: LCDC_HCRCHDR Address: 0xF8038344 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one, this field disables the layer at the end of the current frame. The frame is completed.
PAGE 1096
44.7.90 Hardware Cursor Layer Channel Status Register Name: LCDC_HCRCHSR Address: 0xF8038348 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one, this field disables the layer at the end of the current frame.
PAGE 1097
44.7.91 Hardware Cursor Layer Interrupt Enable Register Name: LCDC_HCRIER Address: 0xF803834C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled.
PAGE 1098
44.7.92 Hardware Cursor Layer Interrupt Disable Register Name: LCDC_HCRIDR Address: 0xF8038350 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled.
PAGE 1099
44.7.93 Hardware Cursor Layer Interrupt Mask Register Name: LCDC_HCRIMR Address: 0xF8038354 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled.
PAGE 1100
44.7.94 Hardware Cursor Layer Interrupt Status Register Name: LCDC_HCRISR Address: 0xF8038358 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one, this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
PAGE 1101
44.7.95 Hardware Cursor Layer Head Register Name: LCDC_HCRHEAD Address: 0xF803835C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor.
PAGE 1102
44.7.96 Hardware Cursor Layer Address Register Name: LCDC_HCRADDR Address: 0xF8038360 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer start address Frame Buffer Start Address.
PAGE 1103
44.7.97 Hardware Cursor Layer Control Register Name: LCDC_HCRCTRL Address: 0xF8038364 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled.
PAGE 1104
44.7.98 Hardware Cursor Layer Next Register Name: LCDC_HCRNEXT Address: 0xF8038368 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address DMA Descriptor next address, this address must be word aligned.
PAGE 1105
44.7.99 Hardware Cursor Layer Configuration 0 Register Name: LCDC_HCRCFG0 Address: 0xF803836C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 – • BLEN: AHB Burst Length Table 44-69. Value Name Description 0 AHB_SINGLE 1 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of four 32-bit data.
PAGE 1106
44.7.100 Hardware Cursor Layer Configuration 1 Register Name: LCDC_HCRCFG1 Address: 0xF8038370 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 7 6 29 – 21 – 13 28 – 20 – 12 5 4 – RGBMODE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 24 – 16 – 8 CLUTMODE 1 – 0 CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color Lookup table is selected. • RGBMODE: RGB input mode selection Table 44-70.
PAGE 1107
44.7.101 Hardware Cursor Layer Configuration 2 Register Name: LCDC_HCRCFG2 Address: 0xF8038374 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XPOS • XPOS: Horizontal Window Position Hardware Cursor Horizontal window position. • YPOS: Vertical Window Position Hardware Cursor Vertical window position.
PAGE 1108
44.7.102 Hardware Cursor Layer Configuration 3 Register Name: LCDC_HCRCFG3 Address: 0xF8038378 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 29 – 21 28 – 20 14 – 6 13 – 5 12 – 4 27 – 19 YSIZE 11 – 3 XSIZE 26 – 18 25 – 17 24 – 16 10 – 2 9 – 1 8 – 0 • XSIZE: Horizontal Window Size Hardware cursor width is limited to 128 pixels. Hardware Cursor window width in pixels. The window width is set to (XSIZE+1).
PAGE 1109
44.7.103 Hardware Cursor Layer Configuration 4 Register Name: LCDC_HCRCFG4 Address: 0xF803837C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
PAGE 1110
44.7.104 Hardware Cursor Layer Configuration 6 Register Name: LCDC_HCRCFG6 Address: 0xF8038384 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the Hardware Cursor DMA channel is disabled. • GDEF: Green Default Default Green color when the Hardware Cursor DMA channel is disabled.
PAGE 1111
44.7.105 Hardware Cursor Layer Configuration 7 Register Name: LCDC_HCRCFG7 Address: 0xF8038388 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY • RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay.
PAGE 1112
44.7.106 Hardware Cursor Layer Configuration 8 Register Name: LCDC_HCRCFG8 Address: 0xF803838C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK • RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared.
PAGE 1113
44.7.107 Hardware Cursor Layer Configuration 9 Register Name: LCDC_HCRCFG9 Address: 0xF8038390 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 OVR 14 – 6 LAEN 13 – 5 GAEN 12 – 4 REVALPHA 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA • CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled.
PAGE 1114
• DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. • REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp, the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp, the pixel is shifted and the least significant bit replicates the MSB.
PAGE 1115
44.7.108 Base CLUT Register x Register Name: LCDC_BASECLUTx [x=0..255] Address: 0xF8038400 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RCLUT GCLUT BCLUT • BCLUT: Blue Color Entry This field indicates the 8 bit width Blue color of the color lookup table. • GCLUT: Green Color Entry This field indicates the 8 bit width Green color of the color lookup table.
PAGE 1116
44.7.109 Overlay 1 CLUT Register x Register Name: LCDC_OVR1CLUTx [x=0..255] Address: 0xF8038800 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT • BCLUT: Blue Color Entry This field indicates the 8-bit width Blue color of the color lookup table. • GCLUT: Green Color Entry This field indicates the 8-bit width Green color of the color lookup table.
PAGE 1117
44.7.110 High End Overlay CLUT Register x Register Name: LCDC_HEOCLUTx [x=0..255] Address: 0xF8039000 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT • BCLUT: Blue Color Entry This field indicates the 8-bit width Blue color of the color lookup table. • GCLUT: Green Color Entry This field indicates the 8-bit width Green color of the color lookup table.
PAGE 1118
44.7.111 Hardware Cursor CLUT Register x Register Name: LCDC_HCRCLUTx [x=0..255] Address: 0xF8039400 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT • BCLUT: Blue Color Entry This field indicates the 8-bit width Blue color of the color lookup table. • GCLUT: Green Color Entry This field indicates the 8-bit width Green color of the color lookup table.
PAGE 1119
45. Electrical Characteristics 45.1 Absolute Maximum Ratings Table 45-1. Absolute Maximum Ratings* Operating Temperature (Industrial)...............-40°C to + 85°C Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . ..................................................125°C Storage Temperature................................... -60°C to + 150°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 1120
Table 45-2. DC Characteristics (Continued) VVDDIOP0 DC Supply Peripheral I/Os 1.65 3.6 V VVDDIOP1 DC Supply Peripheral I/Os 1.65 3.6 V VVDDANA DC Supply Analog 3.0 3.
PAGE 1121
45.3 Power Consumption z Typical power consumption of PLLs, Slow Clock and Main Oscillator. z Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup. z Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 45.3.
PAGE 1122
Table 45-4. Power Consumption by Peripheral in Active Mode Peripheral Consumption PIO Controller 1 USART 6 UHPHS 60 UDPHS 22 ADC 5 TWI 2 SPI 3 PWM 6 HSMCI 28 SSC 5 Timer Counter Channels 12 DMA 1 SMD 14 LCD 30 Note: 1. Unit μA/MHz(1) Reference frequency is peripheral frequency. It can be a division (1,2,4,8) of MCK. Refer to PMC section for more details.
PAGE 1123
45.4 Clock Characteristics 45.4.1 Processor Clock Characteristics Table 45-5. Processor Clock Waveform Parameters Symbol Parameter 1/(tCPPCK) Processor Clock Frequency Conditions VDDCORE = 0.9V T = 85°C Min Max Units 125(1) 400 MHz Min Max Units 125(1) 133 MHz 45.4.2 Master Clock Characteristics Table 45-6. Master Clock Waveform Parameters Symbol Parameter 1/(tCPMCK) Master Clock Frequency Conditions VDDCORE = 0.
PAGE 1124
XIN XOUT GNDPLL 1K CCRYSTAL CLEXT CLEXT 45.5.1 Crystal Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. Table 45-8. Crystal Characteristics Symbol ESR Parameter Equivalent Series Resistor Rs CM Motional Capacitance CS Shunt Capacitance Conditions Min Typ Max @16 MHz 80 @12 MHz CCRYSTAL Max 90 @12 MHz CCRYSTAL Min 110 5 Unit Ω 9 fF 7 pF 45.5.
PAGE 1125
45.6 12 MHz RC Oscillator Characteristics Table 45-10. 12 MHz RC Oscillator Characteristics Symbol Parameter F0 Min Typ Max Units Nominal Frequency 8.4 12 15.6 MHz Duty Duty Cycle 45 50 55 % IDD ON Power Consumption Oscillation 86 140 86 125 tON Startup time 6 10 µs IDD STDBY Standby Consumption 22 µA 45.7 Conditions µA 32 kHz Oscillator Characteristics Table 45-11.
PAGE 1126
45.7.1 32 kHz Crystal Characteristics Table 45-12. 32 kHz Crystal Characteristics Symbol Parameter Conditions Min ESR Equivalent Series Resistor Rs Crystal @ 32.768 kHz CM Motional Capacitance Crystal @ 32.768 kHz CS Shunt Capacitance Crystal @ 32.768 kHz Current dissipation Unit 50 100 kΩ 0.6 3 fF 0.6 2 pF CCRYSTAL32 = 6 pF 0.55 1.3 µA (1) CCRYSTAL32 = 12.5pF 0.85 1.6 µA RS = 50 kΩ (1) CCRYSTAL32 = 6 pF 0.7 2.0 µA (1) CCRYSTAL32 = 12.5 pF 1.1 2.2 µA 0.
PAGE 1127
45.9 PLL Characteristics Table 45-15. PLLA Characteristics Symbol Parameter Conditions Min FOUT Output Frequency Refer to following table FIN Input Frequency IPLL Current Consumption Max Unit 400 800 MHz 2 32 MHz 9 mA 1 µA T Startup Time 50 µs active mode Typ 7 standby mode The following configuration of ICPLLA and OUTA must be done for each PLLA frequency range. Table 45-16.
PAGE 1128
45.10 I/Os Criteria used to define the maximum frequency of the I/Os: z Output duty cycle (40%-60%) z Minimum output swing: 100 mV to VDDIO - 100 mV z Addition of rising and falling time inferior to 75% of the period Table 45-18. I/O Characteristics Symbol Parameter Conditions FreqMax VDDIOP powered Pins frequency Min Max Units 3.3V domain (1) 1.8V domain Notes: 1. 2. MHz (2) MHz 3.3V domain: VVDDIOP from 3.0V to 3.6V, maximum external capacitor = 40 pF 1.8V domain: VVDDIOP from 1.
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45.11.3 Dynamic Power Consumption Table 45-21. Dynamic Power Consumption Symbol Parameter IBIAS Bias current consumption on VBG IVDDUTMII IVDDUTMIC Note: Conditions Min Typ Max Unit 0.7 0.
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45.12 USB Transceiver Characteristics 45.12.1 Electrical Characteristics Table 45-22. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit 0.8 V Input Levels VIL Low Level VIH High Level VDI Differential Input Sensitivity VCM Differential Input Common Mode Range CIN Transceiver capacitance Capacitance to ground on each line I Hi-Z State Data Line Leakage 0V < VIN < 3.
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45.13 Analog-to-Digital Converter (ADC) Table 45-24. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency 10-bit resolution mode Startup Time Return from Idle Mode Track and Hold Acquisition Time (TTH) Conversion Time (TCT) ADC Clock = 13.2 MHz (1) ADC Clock = 13.2 MHz (1) ADC Clock = 5 MHz Typ ADC Clock = 5 MHz Max Units 13.2 MHz 40 μs 0.5 μs 1.74 (1) 4.6 ADC Clock = 13.2 MHz(1) Throughput Rate Note: Min 440 (1) 192 µs kSPS 1.
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Table 45-27. Transfer Characteristics Parameter Min Typ Resolution Max 10 Integral Non-linearity Units bit ±2 LSB ±2 LSB Differential Non-linearity - ADC Clock = 13.2 MHz - ADC Clock = 5 MHz ±0.9 Offset Error ±10 mV - ADC Clock = 13.2 MHz ±3 LSB - ADC Clock = 5 MHz ±2 Gain Error Table 45-28. Pen Detection Sensitivity ADC_ACR [1:0] Resistor (kOhm) 0 200 1 150 2 100 (default) 3 50 The Pen Detection Sensitivity is programmable thanks to an ADC internal resistor.
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45.14.2 Power-Up Sequence Figure 45-3. VDDCORE and VDDIO Constraints at Startup VDD (V) VDDIO VDDIOtyp VDDIO > Voh Voh VDDIO > Vih Vih VDDCORE VDDCOREtyp Vth+ t <--- Tres ---> < T1 > <------------ T2-----------> Core Supply POR Output SLCK VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach their target values prior to the release of POR.
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45.15 SMC Timings 45.15.1 Timing Conditions SMC Timings are given for MAX corners. Timings are given assuming a capacitance load on data, control and address pads: Table 45-29. Capacitance Load Corner Supply MAX MIN 3.3V 50pF 5 pF 1.8V 30 pF 5 pF In the following tables, tCPMCK is MCK period. 45.15.2 Timing Extraction 45.15.2.1Zero Hold Mode Restrictions Table 45-30. Zero Hold Mode Use Maximum system clock frequency (MCK) Symbol Parameter Min VDDIOM supply 1.8V Units 3.
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Table 45-32. SMC Read Signals - NCS Controlled (READ_MODE= 0) Symbol Parameter Min VDDIOM supply Units 1.8V 3.3V NO HOLD SETTINGS (ncs rd hold = 0) SMC8 Data Setup before NCS High SMC9 Data Hold after NCS High 26.9 25.0 ns 0 0 ns 12.3 10.4 ns 0 0 ns (ncs rd setup + ncs rd pulse)* tCPMCK - 18.4 (ncs rd setup + ncs rd pulse)* tCPMCK - 18.
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Table 45-33. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) (Continued) Symbol Parameter Min 1.8V Supply Max 3.3V Supply 1.8 V Supply 3.3 V Supply Units NO HOLD SETTINGS (nwe hold = 0) SMC21 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25, NCS change(1) 1.9 1.5 SMC21b Min Period/Max Frequency with No Hold settings 11.4 9.7 ns 87 103 ns/ MHz Notes: 1. hold length = total cycle duration - setup duration - pulse duration.
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Figure 45-4. SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC26 SMC24 A0/A1/NBS[3:0] /A2-A25 SMC13 SMC13 NRD SMC14 NCS SMC14 SMC9 SMC8 SMC10 SMC23 SMC11 SMC22 SMC26 D0 - D15 SMC27 SMC25 NWE NCS Controlled READ with NO HOLD NCS Controlled READ with HOLD NCS Controlled WRITE Figure 45-5.
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45.16 DDRSDRC Timings The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR modules. DDR2, LP-DDR and SDR timings are specified by the JEDEC standard. Supported speed grade limitations: z DDR2-400 limited at 133 MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#) z LP-DDR limited at 133 MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK) z SDR-100 (3.3V, 50pF on data/control, 10pF on CK) z SDR-133 (3.
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45.17.1.3Timing Extraction Figure 45-6. SPI Master mode 1 and 2 SPCK SPI1 SPI0 MISO SPI2 MOSI Figure 45-7. SPI Master mode 0 and 3 SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 45-8.
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Figure 45-9. SPI Slave mode 1 and 2 NPCS0 SPI13 SPI12 SPCK SPI9 MISO SPI10 SPI11 MOSI Figure 45-10.SPI Slave mode - NPCS timings SPI15 SPI14 SPI6 SPCK (CPOL = 0) SPI12 SPI13 SPI9 SPCK (CPOL = 1) SPI16 MISO Table 45-36. SPI Timings with 3.3V Peripheral Supply Symbol Parameter Cond Min Max Units 66 MHz Master Mode SPISPCK SPI Clock SPI0 MISO Setup time before SPCK rises SPI1 13.
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Table 45-36. SPI Timings with 3.3V Peripheral Supply (Continued) Symbol Parameter Cond Min Max Units SPI7 MOSI Setup time before SPCK rises SPI8 MOSI Hold time after SPCK rises SPI9 SPCK rising to MISO 2.7 SPI10 MOSI Setup time before SPCK falls 1.7 ns SPI11 MOSI Hold time after SPCK falls 0 ns SPI12 NPCS0 setup to SPCK rising 3.8 ns SPI13 NPCS0 hold after SPCK falling 0 ns SPI14 NPCS0 setup to SPCK falling 3.
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Figure 45-11.Min and Max access time for SPI output signal SPCK SPI1 SPI0 MISO SPI2max MOSI SPI2min 45.17.2 SSC 45.17.2.1Timing conditions Timings are given assuming a capacitance load on Table 45-38. Table 45-38. Capacitance Load Corner Supply MAX MIN 3.3V 30pF 5 pF 1.8V 20pF 5 pF 45.17.2.2Timing Extraction Figure 45-12.
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Figure 45-13.SSC Transmitter, TK in input and TF in output TK (CKI =0) TK (CKI =1) SSC1 TF/TD Figure 45-14.SSC Transmitter, TK in output and TF in input TK (CKI=0) TK (CKI=1) SSC2 SSC3 TF SSC4 TD Figure 45-15.
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Figure 45-16.SSC Receiver RK and RF in input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 45-17.SSC Receiver, RK in input and RF in output RK (CKI=1) RK (CKI=0) SSC8 SSC9 RD SSC10 RF Figure 45-18.
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Figure 45-19.SSC Receiver, RK in ouput and RF in input RK (CKI=0) RK (CKI=1) SSC12 SSC11 RF/RD Table 45-39. SSC Timings Symbol Parameter Cond Min Max 1.8V domain(3) -5.6 5.8 (4) 3.3V domain -4.6 4.9 1.8V domain(3) 3.0 15.7 3.3V domain(4) 2.3 11.4 1.8V domain(3) 14.0 3.3V domain(4) 9.9 1.
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Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7 (Receive Start Selection), two Periods of the MCK must be added to timings. 2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or RK) edge and the signal change. The Max access time is the time between the TK edge and the signal stabilization. Figure 45-20 illustrates Min and Max accesses for SSC0.
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45.17.4.2Timing extraction Figure 45-21.USART SPI Master Mode NSS SPI5 SPI3 CPOL=1 SPI0 SCK CPOL=0 SPI4 MISO SPI4 SPI1 SPI2 LSB MSB MOSI Figure 45-22.
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Figure 45-23.USART SPI Slave mode: (Mode 0 or 3) NSS SPI14 SPI15 SCK SPI9 MISO SPI10 SPI11 MOSI Table 45-41. USART SPI Timings Symbol Parameter Conditions Min Max Units Master Mode SPI0 SCK Period SPI1 Input Data Setup Time SPI2 Input Data Hold Time SPI3 Chip Select Active to Serial Clock SPI4 Output Data Setup Time SPI5 Serial Clock to Chip Select Inactive 1.8v domain(1) 3.3v domain(2) MCK/6 ns 1.8v domain(1) 0.5 * MCK + 4.1 (2) 0.5 * MCK + 3.8 1.8v domain(1) 1.
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Table 45-41. USART SPI Timings (Continued) Symbol Parameter SPI10 MOSI Setup time before SCK falls SPI11 MOSI Hold time after SCK falls SPI12 NPCS0 setup to SCK rising SPI13 NPCS0 hold after SCK falling SPI14 NPCS0 setup to SCK falling SPI15 NPCS0 hold after SCK rising Conditions Min Max 1.8v domain (1) 2 * MCK + 2.9 3.3v domain (2) 2 * MCK + 2.8 1.8v domain(1) 2.1 (2) 1.8 3.3v domain 2.5 * MCK + 1.4 (2) 2.5 * MCK + 1.2 1.8v domain(1) 1.5 * MCK + 2.5 (2) 1.5 * MCK + 2.2 1.
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46. Mechanical Overview 46.1 217-ball BGA Package Figure 46-1.
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Table 46-1. Device and 217-ball BGA Package Maximum Weight 450 mg Table 46-2. 217-ball BGA Package Characteristics Moisture Sensitivity Level 3 Table 46-3. Package Reference JEDEC Drawing Reference MO-205 JESD97 Classification e1 Table 46-4. Package Information Ball Land 0.43 mm ± 0.05 Solder Mask Opening 0.30 mm ± 0.05 46.2 Marking All devices are marked with the Atmel logo and the ordering code.
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47. SAM9G15 Ordering Information Table 47-1.
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48. SAM9G15 Errata 48.1 External Bus Interface (EBI) 48.1.1 EBI: Data lines are Hi-Z after reset Data lines are Hi-Z after reset. This does not affect boot capabilities neither on NOR nor on NAND memories. Problem Fix/Workaround None. 48.2 Reset Controller (RSTC) 48.2.1 RSTC: Reset during SDRAM Accesses When a Reset (user reset, watchdog, software reset) occurs during SDRAM read access, the SDRAM clock is turned off while data is ready to be read on the data bus.
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48.4 USB High Speed Host Port (UHPHS) and Device Port (UDPHS) 48.4.1 UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL The DLL used to oversample the incoming bitstream may not lock in the correct phase, leading to a bad reception of the incoming packets. This issue may occur after the USB device resumes from the Suspend mode. The DLL is used only in the High Speed mode, meaning the Full Speed mode is not impacted by this issue.
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Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during the document review and approval loop. Doc. Rev. Comments 11052D Change Request Ref. Introduction: Section 6.3.3 “DDR2SDR Controller”, replaced LPDDR2 with LPDDR. 8146 Added “Write Protected Registers” in the peripherals list in “Features” . 8213 Added “4-bank” references to the DDR2 characteristics in “Features” , Section 1. “Description” and Section 6.3.
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Doc. Rev. Comments 11052D Change Request Ref. WDT: Added the 4th paragraph “If the watchdog is restarted...” in Section 17.4 “Functional Description”. 8128: Section 17.5.3 “Watchdog Timer Status Register”, added a note in “WDERR: Watchdog Error” . Updated Section 17.2 “Embedded Characteristics”. 8218 SHDWC: Removed AMBA references from Section 18.2 “Embedded Characteristics”. rfo Section 18.3 “Block Diagram”, removed redundant Figure 18-2. Sutdown Controller Block Diagram. 8454 GPBR: Section 19.3.
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Doc. Rev. Comments 11052D Change Request Ref. PMECC: Figure 27-2 “Software/Hardware Multibit Error Correction Dataflow”, “READ PAGE” and “PROGRAM PAGE” positions swapped in the flow chart. 7495 Figure 27-5 “Read Operation with Spare Decoding”, configuration revised as ”...SPAREEN set to One and AUTO set to Zero.” Section 27.2 “Embedded Characteristics”, added a line about supporting 8-bit Nand Flash data bus. 8403 Section 27.6.
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Doc. Rev. Comments 11052D Change Request Ref. UDPHS: Section 32.4 “Typical Connection”, completed a note below Figure 32-2 “Board Schematic”. 7986 Section 32.7 “USB High Speed Device Port (UDPHS) User Interface”, removed duplicated names in fields and created separated view for UDPHS Control and Status Registers in: 8396 - Section 32.7.9 “UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)” - Section 32.7.
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Doc. Rev. Comments 11052D Change Request Ref. SPI: Replaced references to “Advanced Interrupt Controller” with “Interrupt Controller”. 7513 Section 35.8.9 “SPI Chip Select Register”, added a phrase specifying when this register can be written and updated the table in “BITS: Bits Per Transfer” : reserved bits are from 9 to 15. 7931 Section 35.7.3.5 “Peripheral Selection”, corrected a cross-reference for the footnote. 8025 Section 35.8.
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Doc. Rev. Comments 11052D Change Request Ref. USART: Section 39.7.3.4 “Manchester Decoder”, added a paragraph “In order to increase the compatibility...”. 8012 Section 39.8 “Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface”: - updated the reset value of the US_MAN register from ‘0x30011004’ to ‘0xB0011004’ in Table 39-16 “Register Mapping” - updated descriptions of US_CR, US_MR, US_IER, US_IDR, US_IMR, and US_CSR registers in: Section 39.8.
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Doc. Rev. Comments 11052D Change Request Ref. ADC: Section 41.8.15 “ADC Compare Window Register”, added two paragraphs about programming LOWTHRES and 8045 HIGHTHRES bitfields depending on the LOWRES bitfield settings (ADC Mode Register). Increased the size of XPOS/XSCALE/YPOS/YSCALE fields from 10 to 12-bit in Section 41.8.19 “ADC 8229 Touchscreen X Position Register”, Section 41.8.20 “ADC Touchscreen Y Position Register” and Section 41.8.21 “ADC Touchscreen Pressure Register”. Section 41.6.
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Doc. Rev. Comments 11052C Change Request Ref. HSMCI: 8074 Added missing component. Doc. Rev. Comments 11052B Change Request Ref. System Controller: rfo Figure 7-1, “SAM9G15 System Controller Block Diagram” , DDR sysclk --> DDRCK. ADC: 7987 Section 41.1 “Description” updated to show Touchscreen information. DMAC: FIFO size table removed from Section 31.1 “Description”, as the size depends on DMAC0 (see Section 31.2.1 “DMA Controller 0”) and DMAC1 (see Section 31.2.2 “DMA Controller 1”).
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Doc. Rev. Comments 11052A Change Request Ref.
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Table of Contents Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . .
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11.3 11.4 11.5 Chip Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 NVM Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SAM-BA Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12. Boot Sequence Controller (BSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.1 12.2 12.3 12.4 Description . . . . . . . . . . . . . .
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18. Shutdown Controller (SHDWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 18.1 18.2 18.3 18.4 18.5 18.6 18.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . .
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24. Debug Unit (DBGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 24.1 24.2 24.3 24.4 24.5 24.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . .
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29.11 29.12 29.13 29.14 29.15 29.16 Data Float Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable IO Delays . . . . . . . . . . . . . . . .
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34.10 34.11 34.12 34.13 34.14 CE-ATA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSMCI Boot Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSMCI Transfer Done Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Speed MultiMedia Card Interface (HSMCI) User Interface . . . . . . . . .
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39.3 39.4 39.5 39.6 39.7 39.8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . .
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45. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119 45.1 45.2 45.3 45.4 45.5 45.6 45.7 45.8 45.9 45.10 45.11 45.12 45.13 45.14 45.15 45.16 45.17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.