Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller BGA 217 (15x15) 16/32-Bit 190 MHz I/O number 96

NOTE: This is a summary document.

The complete document is available on

the Atmel website at www.atmel.com.

Features

• Incorporates the ARM926EJ-S™ ARM

Thumb

Processor

– DSP Instruction Extensions

– ARM Jazelle

Technology for Java

Acceleration

– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer

– 210 MIPS at 190 MHz

– Memory Management Unit

– EmbeddedICE

™

, Debug Communication Channel Support

– Mid-level implementation Embedded Trace Macrocell

™

• Additional Embedded Memories

– 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed

– 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus

Speed

• External Bus Interface (EBI)

– Supports SDRAM, Static Memory, NAND Flash and CompactFlash

• LCD Controller

– Supports Passive or Active Displays

– Up to 16-bits per Pixel in STN Color Mode

– Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048

• USB

– USB 2.0 Full Speed (12 Mbits per second) Host Double Port

• Dual On-chip Transceivers

• Integrated FIFOs and Dedicated DMA Channels

– USB 2.0 Full Speed (12 Mbits per second) Device Port

• On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs

• Bus Matrix

– Handles Five Masters and Five Slaves

– Boot Mode Select Option

– Remap Command

• Fully Featured System Controller (SYSC) for Efficient System Management, including

– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a

Total of 16 Bytes

– Clock Generator and Power Management Controller

– Advanced Interrupt Controller and Debug Unit

– Periodic Interval Timer, Watchdog Timer and Real-time Timer

– Three 32-bit PIO Controllers

• Reset Controller (RSTC)

– Based on Power-on Reset Cells, Reset Source Identification and Reset Output

Control

• Shutdown Controller (SHDWC)

– Programmable Shutdown Pin Control and Wake-up Circuitry

• Clock Generator (CKGR)

– 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a

Permanent Slow Clock

– 3 to 20 MHz On-chip Oscillator and two PLLs

• Power Management Controller (PMC)

– Very Slow Clock Operating Mode, Software Programmable Power Optimization

Capabilities

– Four Programmable External Clock Signals

AT91 ARM

Thumb-based

Microcontrollers

AT91SAM9261

Summary

6062LS–ATARM–23-Mar-09

Summary of content (44 pages)

PAGE 1
Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 210 MIPS at 190 MHz – Memory Management Unit – EmbeddedICE™, Debug Communication Channel Support – Mid-level implementation Embedded Trace Macrocell™ Additional Embedded Memories – 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed – 160 Kbytes of Internal SRA
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• Advanced Interrupt Controller (AIC) • • • • • • • • • • • • • • • 2 – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention – Mode for General Purpose Two-wire UART Serial Communication Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter Watch
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AT91SAM9261 1. Description The AT91SAM9261 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays.
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2.
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AT91SAM9261 3. Signal Description Table 3-1. Signal Description by Peripheral Signal Name Function Type Active Level Comments Power VDDIOM EBI I/O Lines Power Supply Power 1.65 V to 1.95V and 3.0V to 3.6V VDDIOP Peripherals I/O Lines Power Supply Power 2.7V to 3.6V VDDBU Backup I/O Lines Power Supply Power 1.08V to 1.32V VDDPLL PLL Power Supply Power 3.0V to 3.6V VDDOSC Oscillator Power Supply Power 3.0V to 3.6V VDDCORE Core Chip Power Supply Power 1.08V to 1.
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Table 3-1. Signal Description by Peripheral (Continued) Signal Name Function Type NRST Microcontroller Reset TST Test Mode Select Input BMS Boot Mode Select Input Active Level Comments Reset/Test I/O Low Pull-up resistor Pull-down resistor.
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AT91SAM9261 Table 3-1.
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Table 3-1.
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AT91SAM9261 4. Package and Pinout The AT91SAM9261 is available in a 217-ball LFBGA RoHS-compliant package, 15 x 15 mm, 0.8 mm ball pitch 4.1 217-ball LFBGA Package Outline Figure 4-1 shows the orientation of the 217-ball LFBGA Package. A detailed mechanical description is given in the section “AT91SAM9261 Mechanical Characteristics” of the product datasheet. Figure 4-1.
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4.2 Pinout AT91SAM9261 Pinout for 217-ball LFBGA Package (1) Table 4-1.
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AT91SAM9261 5. Power Considerations 5.1 Power Supplies The AT91SAM9261 has six types of power supply pins: • VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges from 1.65V to 1.95V and 3.0V to 3.6V, 1.8V and 3.3V nominal. • VDDIOP pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 2.7V and 3.6V, 3.3V nominal.
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6.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. 6.3 Reset Pin NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP.
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AT91SAM9261 7. Processor and Architecture 7.
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7.
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AT91SAM9261 7.4 Peripheral DMA Controller • Transfers from/to peripheral to/from any memory space without intervention of the processor. • Next Pointer Support, forbids strong real-time constraints on buffer management.
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8. Memories Figure 8-1.
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AT91SAM9261 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7.
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8.1.1 Internal Memory Mapping Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset. Table 8-3. Address Internal Memory Mapping Master 0: ARM926 Instruction REMAP(RCB0) = 0 0x0000 0000 Note: BMS = 1 BMS = 0 Int. ROM EBI NCS0(1) Master 1: ARM926 Data REMAP (RCB0) = 1 Int. RAM C REMAP (RCB1) = 0 REMAP (RCB1) = 1 BMS = 1 BMS = 0 Int. ROM EBI NCS0(1) Int. RAM C 1. EBI NCS0 is to be connected to a 16-bit non-volatile memory.
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AT91SAM9261 The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user dynamically changes the Internal SRAM configuration, the new 16 Kbyte block organization may affect the previous configuration from a software point of view. Table 8-5 illustrates different configurations and the related 16 Kbyte blocks (RB0 to RB9) assignments. Table 8-5.
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8.1.2 Boot Strategies The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted for each Master of the Bus Matrix. Refer to the Bus Matrix Section for more details. When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory.
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AT91SAM9261 8.1.3 ETM™ Memories The eight ETM9 Medium+ memory map decoder inputs are connected to custom address decoders and the resulting memory mapping is summarized in Table 8-6. Table 8-6. 8.
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9. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Peripherals are all mapped within the highest 6 Kbytes of address space, between addresses 0xFFFF EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 9-1 on page 23 shows the System Controller block diagram.
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AT91SAM9261 9.1 Block Diagram Figure 9-1. System Controller Block Diagram System Controller irq0-irq2 fiq nirq nfiq Advanced Interrupt Controller periph_irq[2..
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9.2 Reset Controller • Based on two Power-on-Reset cells • Status of the last reset – Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset • Controls the internal resets and the NRST pin output 9.3 Shutdown Controller • Shutdown and Wake-up logic: – Software programmable assertion of the SHDN pin – Deassertion Programmable on a WKUP pin level change or on alarm 9.4 General-purpose Backup Registers • Four 32-bit general-purpose backup registers 9.
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AT91SAM9261 9.6 Power Management Controller • The Power Management Controller provides: – the Processor Clock PCK – the Master Clock MCK – the USB Clock USBCK (HCK0) – the LCD Controller Clock LCDCK (HCK1) – up to thirty peripheral clocks – four programmable clock outputs: PCK0 to PCK3 Figure 9-3. Power Management Controller Block Diagram Processor Clock Controller int Master Clock Controller SLCK MAINCK PLLACK PLLBCK PCK Idle Mode Divider /1,/2,/4 Prescaler /1,/2,/4,...
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9.10 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.
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AT91SAM9261 – Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of peripherals • ICE Access prevention – Enables software to prevent system access through the ARM Processor’s ICE – Prevention is made by asserting the NTRST line of the ARM Processor’s ICE 9.
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10. Peripherals 10.1 User Interface The User Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 16. 10.2 Peripheral Identifiers Table 10-1 defines the Peripheral Identifiers of the AT91SAM9261.
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AT91SAM9261 10.3 Peripheral Multiplexing on PIO Lines The AT91SAM9261 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions, A or B. Table 10-2 on page 31, Table 10-3 on page 32 and Table 10-4 on page 33 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers.
PAGE 30
• using the three Timer Counter channels’ outputs and trigger inputs • using the SSC2 10.3.1.5 NAND Flash Interface Using the NAND Flash interface prevents: • using NCS3, NCS6 and NCS7 to access other parallel devices 10.3.1.6 Compact Flash Interface Using the CompactFlash interface prevents: • using NCS4 and/or NCS5 to access other parallel devices 10.3.1.7 SPI0 and the MultiMedia Card Interface As the DataFlash Card is compatible with the SDCard, it is useful to multiplex SPI and MCI.
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AT91SAM9261 10.3.2 PIO Controller A Multiplexing Table 10-2.
PAGE 32
10.3.3 PIO Controller B Multiplexing Table 10-3.
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AT91SAM9261 10.3.4 PIO Controller C Multiplexing Table 10-4.
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10.3.5 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-Time Timer • the Watchdog Timer • the Reset Controller • the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.3.6 10.4 External Interrupts All external interrupt signals, i.e.
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AT91SAM9261 10.
PAGE 36
10.
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AT91SAM9261 • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.10 Synchronous Serial Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader and more). • Contains an independent receiver and transmitter and a common clock divider. • Offers a configurable frame sync and data length.
PAGE 38
10.13 USB • USB Host Port: – Compliance with Open HCI Rev 1.0 specification – Compliance with USB V2.0 Full-speed and Low-speed Specification – Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices – Root hub integrated with two downstream USB ports – Two embedded USB transceivers – No overcurrent detection – Supports power management – Operates as a master on the Bus Matrix • USB Device Port: – USB V2.0 full-speed compliant, 12 Mbits per second – Embedded USB V2.
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AT91SAM9261 11. Package Drawing Figure 11-1.
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12. Ordering Information Table 12-1.
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AT91SAM9261 13. Revision History Table 13-1. Doc. Rev. Revision History Source 6062AS Comments Qualified/Internal: 23-Aug-04 Date: 02-Jun-05 CSR 04-370 Change to Additional Embedded Memories in “Features” on page 1. Change to Section 5.2 “Power Consumption” on page 11. Change to Table 8-3 on page 18. CSR 04-371 Change to AIC, “Features” on page 1, SMCS signal added to Table 3-1, “Signal Description by Peripheral,” on page 5, Change to Section 10.3.1.5 “NAND Flash Interface” on page 30.
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Table 13-1. Doc. Rev. Revision History (Continued) Source Comments Corrected MIPS and speed on page 1. 6062DS 2292 Added information on EBI NCS0 hwhen BMS = 0 in Table 8-3, “Internal Memory Mapping,” on page 18. 2946 Updated information on JTAGSEL in Section 3-1 “Signal Description by Peripheral” on page 5 and in Section 6.1 “JTAG Port Pins” on page 11. 2475 Reformatted Section 8. “Memories” on page 16.
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AT91SAM9261 Table 13-1. Doc. Rev. Revision History (Continued) Source Comments 5846 In Features, on page 2 Debug Unit (DBGU) updated Section 10.9 “USART”, manchester encoding option is not avaiilable. 6062KS 5932 5424/rfo 6062LS Section 8.1.2.1 “BMS = 1, Boot on Embedded ROM”, updated. Section 12. “Ordering Information”, updated with ordering information for chip revision B.
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