Datasheet

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6062LS–ATARM–23-Mar-09
AT91SAM9261
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
• Chip ID Registers
– Identification of the device revision, sizes of the embedded memories, set of
peripherals
• ICE Access prevention
– Enables software to prevent system access through the ARM Processor’s ICE
– Prevention is made by asserting the NTRST line of the ARM Processor’s ICE
9.12 PIO Controllers
• Three PIO Controllers, each controlling up to 32 programmable I/O Lines
– PIOA has 32 I/O Lines
– PIOB has 32 I/O Lines
– PIOC has 32 I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O)
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write