Datasheet

17
6062LS–ATARM–23-Mar-09
AT91SAM9261
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to
8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7.
The area 0 is reserved for the addressing of the internal memories, and a second level of decod-
ing provides 1 Mbyte of internal memory area. The area 15 is reserved for the peripherals and
provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
The Bus Matrix manages five Masters and five Slaves.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master.
Regarding Master 0 and Master 1 (ARM926
™
Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap. Refer to Table 8-3 for details.
Each Slave has its own arbiter, thus allowing a different arbitration per Slave.
8.1 Embedded Memories
• 32 KB ROM
– Single Cycle Access at full bus speed
• 160 KB Fast SRAM
– Single Cycle Access at full bus speed
– Supports ARM926EJ-S TCM interface at full processor speed
Table 8-1. List of Bus Matrix Masters
Master 0 ARM926 Instruction
Master 1 ARM926 Data
Master 2 PDC
Master 3 LCD Controller
Master 4 USB Host
Table 8-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1 Internal ROM
Slave 2 LCD Controller and USB Host Port Interfaces
Slave 3 External Bus Interface
Slave 4 Internal Peripherals