Datasheet

30
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
Note: Setting AIC, SYSC, UHP and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect.
10.2.1 Peripheral Interrupts and Clock Control
10.2.1.1 System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
z the SDRAM Controller
z the Debug Unit
z the Periodic Interval Timer
z the Real-time Timer
z the Watchdog Timer
z the Reset Controller
z the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt
Controller.
10.2.1.2 External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated
Peripheral ID. However, there is no clock control associated with these peripheral IDs.
10.3 Peripheral Signal Multiplexing on I/O Lines
The SAM9260 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. Table
10-2 on page 31, Table 10-3 on page 32 and Table 10-4 on page 33 define how the I/O lines of the peripherals A and B
are multiplexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for
the user’s own comments; they may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only might be duplicated within both tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O appears, the
PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is
released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets
low.
If a signal name appears in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit
in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the
pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case.
29 AIC Advanced Interrupt Controller IRQ0
30 AIC Advanced Interrupt Controller IRQ1
31 AIC Advanced Interrupt Controller IRQ2
Table 10-1. SAM9260 Peripheral Identifiers (Continued)
Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt