Datasheet

SAM9260 [SUMMARY]

6221LS–ATARM–15-Oct-12

z 8-level Priority Controller

z Drives the Normal Interrupt of the processor

z Handles priority of the interrupt sources 1 to 31

z Higher priority interrupts can be served during service of lower priority interrupt

z Vectoring

z Optimizes Interrupt Service Routine Branch and Execution

z One 32-bit Vector Register per interrupt source

z Interrupt Vector Register reads the corresponding current Interrupt Vector

z Protect Mode

z Easy debugging by preventing automatic operations when protect models are enabled

z Fast Forcing

z Permits redirecting any normal interrupt source on the Fast Interrupt of the processor

9.11 Debug Unit

z Composed of two functions:

z Two-pin UART

z Debug Communication Channel (DCC) support

z Two-pin UART

z Implemented features are 100% compatible with the standard Atmel

USART

z Independent receiver and transmitter with a common programmable Baud Rate Generator

z Even, Odd, Mark or Space Parity Generation

z Parity, Framing and Overrun Error Detection

z Automatic Echo, Local Loopback and Remote Loopback Channel Modes

z Support for two PDC channels with connection to receiver and transmitter

z Debug Communication Channel Support

z Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE

Interface

9.12 Chip Identification

z Chip ID: 0x019803A2

z JTAG ID: 0x05B1303F

z ARM926 TAP ID: 0x0792603F