Datasheet

SAM9260 [SUMMARY]

6221LS–ATARM–15-Oct-12

9.2 Reset Controller

z Based on two Power-on-reset cells

z One on VDDBU and one on VDDCORE

z Status of the last reset

z Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or

watchdog reset

z Controls the internal resets and the NRST pin output

z Allows shaping a reset signal for the external devices

9.3 Shutdown Controller

z Shutdown and Wake-up logic

z Software programmable assertion of the SHDN pin

z Deassertion Programmable on a WKUP pin level change or on alarm

9.4 Clock Generator

z Embeds a Low-power 32,768 Hz Slow Clock Oscillator and a Low-power RC oscillator selectable with OSCSEL

signal

z Provides the permanent Slow Clock SLCK to the system

z Embeds the Main Oscillator

z Oscillator bypass feature

z Supports 3 to 20 MHz crystals

z Embeds 2 PLLs

z PLLA outputs 80 to 240 MHz clock

z PLLB outputs 70 to 130 MHz clock

z Both integrate an input divider to increase output accuracy

z PLLB embeds its own filter