Datasheet

SAM9260 [SUMMARY]

6221LS–ATARM–15-Oct-12

z Asynchronous read in Page Mode supported (4- up to 32-byte page size)

z Multiple device adaptability

z Compliant with LCD Module

z Control signals programmable setup, pulse and hold time for each Memory Bank

z Multiple Wait State Management

z Programmable Wait State Generation

z External Wait Request

z Programmable Data Float Time

z Slow Clock mode supported

8.2.3 SDRAM Controller

z Supported devices

z Standard and Low-power SDRAM (Mobile SDRAM)

z Numerous configurations supported

z 2K, 4K, 8K Row Address Memory Parts

z SDRAM with two or four Internal Banks

z SDRAM with 16- or 32-bit Datapath

z Programming facilities

z Word, half-word, byte access

z Automatic page break when Memory Boundary has been reached

z Multibank Ping-pong Access

z Timing parameters specified by software

z Automatic refresh operation, refresh rate is programmable

z Energy-saving capabilities

z Self-refresh, power down and deep power down modes supported

z Error detection

z Refresh Error Interrupt

z SDRAM Power-up Initialization by software

z CAS Latency of 1, 2 and 3 supported

z Auto Precharge Command not used

8.2.4 Error Corrected Code Controller

z Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select

z Single bit error correction and 2-bit Random detection

z Automatic Hamming Code Calculation while writing

z ECC value available in a register

z Automatic Hamming Code Calculation while reading

z Error Report, including error flag, correctable error flag and word address being detected erroneous

z Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages