Datasheet

SAM9260 [SUMMARY]

6221LS–ATARM–15-Oct-12

7.3 Peripheral DMA Controller

z Acting as one Matrix Master

z Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor.

z Next Pointer Support, forbids strong real-time constraints on buffer management.

z Twenty-two channels

z Two for each USART

z Two for the Debug Unit

z Two for each Serial Synchronous Controller

z Two for each Serial Peripheral Interface

z One for Multimedia Card Interface

z One for Analog-to-Digital Converter

The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to

High priorities):

z DBGU Transmit Channel

z USART5 Transmit Channel

z USART4 Transmit Channel

z USART3 Transmit Channel

z USART2 Transmit Channel

z USART1 Transmit Channel

z USART0 Transmit Channel

z SPI1 Transmit Channel

z SPI0 Transmit Channel

z SSC Transmit Channel

z DBGU Receive Channel

z USART5 Receive Channel

z USART4 Receive Channel

z USART3 Receive Channel

z USART2 Receive Channel

z USART1 Receive Channel

z USART0 Receive Channel

z ADC Receive Channel

z SPI1 Receive Channel

z SPI0 Receive Channel

z SSC Receive Channel

z MCI Transmit/Receive Channel

Internal ROM X X X - -

UHP User InterfaceX ----

3External Bus InterfaceX XXXX

4 Internal Peripherals X X X - -

Table 7-3. SAM9260 Masters to Slaves Access (Continued)