AT91SAM ARM-based Embedded MPU SAM9260 Features • 180 MHz ARM926EJ-S™ ARM® Thumb® Processor – 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU • Memories • • • • – 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC – Two 4-kbyte internal SRAM, single-cycle access at system speed – One 32-kbyte internal ROM, embedding bootstrap routine Peripherals – ITU-R BT.
1. Description The SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The SAM9260 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses.
PIT MCI RSTC SHDWC RTT 4GPREG PDC POR VDDCORE NRST POR OSC RC WDT OSC PLLB PLLA PMC PDC DBGU AIC System Controller SHDN WKUP VDDBU OSCSEL XIN32 XOUT32 XIN XOUT PLLRCA DRXD DTXD PCK0-PCK1 FIQ IRQ0-IRQ2 TST SLAVE TWI PIOC PIOB PIOA PDC USART0 USART1 USART2 USART3 USART4 USART5 APB JT AG SE L NT R TD ST TDI TMO TC S RTK CK SPI0_, SPI1_ MMU TC0 TC1 TC2 Fast SRAM 4 Kbytes Bus Interface PDC SPI0 SPI1 ROM 32 Kbytes I ICache 8 Kbytes D TC3 TC4 TC5 Fast SRAM 4 Kbytes
3. Signal Description Table 3-1. Signal Description List Signal Name Function Type Active Level Comments Power Supplies VDDIOM EBI I/O Lines Power Supply Power 1.65V to 1.95V or 3.0V to3.6V VDDIOP0 Peripherals I/O Lines Power Supply Power 3.0V to 3.6V VDDIOP1 Peripherals I/O Lines Power Supply Power 1.65V to 3.6V VDDBU Backup I/O Lines Power Supply Power 1.65V to 1.95V VDDANA Analog Power Supply Power 3.0V to 3.6V VDDPLL PLL Power Supply Power 1.65V to 1.
Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level I/O Low Comments Reset/Test NRST Microcontroller Reset TST Test Mode Select Input BMS Boot Mode Select Input Pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. No pull-up resistor BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP0.
Table 3-1.
Table 3-1.
Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments Image Sensor Interface ISI_D0-ISI_D11 Image Sensor Data Input ISI_MCK Image Sensor Reference Clock ISI_HSYNC Image Sensor Horizontal Synchro Input ISI_VSYNC Image Sensor Vertical Synchro Input ISI_PCK Image Sensor Data clock Input Output Provided by PCK1.
4. Package and Pinout The SAM9260 is available in two packages: z 208-pin PQFP Green package (0.5mm pitch). z 217-ball LFBGA Green package (0.8 mm ball pitch).
4.1 208-pin PQFP Package Figure 11-3 shows the orientation of the 208-pin PQFP package. A detailed mechanical description is given in the section “SAM9260 Mechanical Characteristics” of the datasheet. 4.2 208-pin PQFP Pinout Table 4-1.
4.3 217-ball LFBGA Package Figure 11-1 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in the section “SAM9260 Mechanical Characteristics” of the datasheet. 4.4 217-ball LFBGA Pinout Table 4-2.
5. Power Considerations 5.1 Power Supplies The SAM9260 has several types of power supply pins: z VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal. z VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The expected voltage range is selectable by software.
6. I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. The NTRST signal is described in Section 6.3.
6.7 Slow Clock Selection The SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the on-chip RC oscillator. Table 6-1 defines the states for OSCSEL signal. Table 6-1. Slow Clock Selection OSCSEL Slow Clock Startup Time 0 Internal RC 240 µs 1 External 32768 Hz 1200 ms The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The 32,768 Hz startup delay is 1200 ms whereas it is 240 µs for the internal RC oscillator (refer to Table 6-1).
7. Processor and Architecture 7.1 ARM926EJ-S Processor z RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration z Two Instruction Sets ARM High-performance 32-bit Instruction Set z Thumb High Code Density 16-bit Instruction Set z DSP Instruction Extensions z 5-Stage Pipeline Architecture: z z z z 7.
z z 7.2.1 Boot Mode Select z Non-volatile Boot Memory can be internal or external z Selection is made by BMS pin sampled at reset Remap Command z Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory z Allows Handling of Dynamic Exception Vectors Matrix Masters The Bus Matrix of the SAM9260 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available.
Table 7-3. Internal ROM X X X - - UHP User Interface X - - - - 3 External Bus Interface X X X X X 4 Internal Peripherals X X X - - 2 7.3 SAM9260 Masters to Slaves Access (Continued) Peripheral DMA Controller z Acting as one Matrix Master z Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. z Next Pointer Support, forbids strong real-time constraints on buffer management.
7.4 Debug and Test Features z z z ARM926 Real-time In-circuit Emulator z Two real-time Watchpoint Units z Two Independent Registers: Debug Control Register and Debug Status Register z Test Access Port Accessible through JTAG Protocol z Debug Communications Channel Debug Unit z Two-pin UART z Debug Communication Channel Interrupt Handling z Chip ID Register IEEE1149.
8. Memories Figure 8-1.
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7.
z Downloads and runs an application from external storage media into internal SRAM z Downloaded code size depends on embedded SRAM size z Automatic detection of valid application z Bootloader on a non-volatile memory z z SPI DataFlash® connected on NPCS0 and NPCS1 of the SPI0 z 8-bit and/or 16-bit NAND Flash SAM-BA® Monitor in case no valid program is detected in external NVM, supporting z Serial communication on a DBGU z USB Device Port 8.1.1.
z z z z 8.2.
9. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration.
9.1 System Controller Block Diagram Figure 9-1. SAM9260 System Controller Block Diagram System Controller VDDCORE Powered irq0-irq2 fiq periph_irq[2..
9.2 Reset Controller z Based on two Power-on-reset cells z z Status of the last reset z z Allows shaping a reset signal for the external devices Shutdown Controller z 9.4 Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset Controls the internal resets and the NRST pin output z 9.
Figure 9-2. Clock Generator Block Diagram Clock Generator OSC_SEL On Chip RC OSC XIN32 Slow Clock SLCK Slow Clock Oscillator XOUT32 XIN Main Oscillator Main Clock MAINCK PLL and Divider A PLLA Clock PLLACK PLL and Divider B PLLB Clock PLLBCK XOUT PLLRCA Status Control Power Management Controller 9.
Figure 9-3. SAM9260 Power Management Controller Block Diagram Processor Clock Controller int Master Clock Controller SLCK MAINCK PLLACK PLLBCK PCK Idle Mode Divider /1,/2,/4 Prescaler /1,/2,/4,...,/64 MCK Peripherals Clock Controller periph_clk[..] ON/OFF Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] USB Clock Controller ON/OFF PLLBCK 9.6 9.7 9.8 9.
z z 8-level Priority Controller z Drives the Normal Interrupt of the processor z Handles priority of the interrupt sources 1 to 31 z Higher priority interrupts can be served during service of lower priority interrupt Vectoring z Optimizes Interrupt Service Routine Branch and Execution z One 32-bit Vector Register per interrupt source z Interrupt Vector Register reads the corresponding current Interrupt Vector z Protect Mode z Fast Forcing z z 9.
10. Peripherals 10.1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 19. 10.2 Identifiers Table 10-1 defines the Peripheral Identifiers of the SAM9260.
Table 10-1. SAM9260 Peripheral Identifiers (Continued) Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt 29 AIC Advanced Interrupt Controller IRQ0 30 AIC Advanced Interrupt Controller IRQ1 31 AIC Advanced Interrupt Controller IRQ2 Note: Setting AIC, SYSC, UHP and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. 10.2.1 Peripheral Interrupts and Clock Control 10.2.1.
10.3.1 PIO Controller A Multiplexing Table 10-2.
10.3.2 PIO Controller B Multiplexing Table 10-3.
10.3.3 PIO Controller C Multiplexing Table 10-4.
10.4 Embedded Peripherals 10.4.
Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these USARTs, the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem signals are never activated. 10.4.4 Serial Synchronous Controller z Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.
z Root hub integrated with two downstream USB ports in the 217-LFBGA package z Two embedded USB transceivers z Supports power management z Operates as a master on the Matrix 10.4.8 USB Device Port z USB V2.0 full-speed compliant, 12 MBits per second z Embedded USB V2.
z Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger z Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels z Four analog inputs shared with digital signals SAM9260 [SUMMARY] 6221LS–ATARM–15-Oct-12 37
11. SAM9260 Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 217-ball LFBGA: Ball A1 Position One or two ink (or laser) dots may be present on top of the package. Optional. Atmel internal use Only. Figure 11-2.
Table 11-1. 217-ball LFBGA Soldering Information Ball Land 0.43 mm +/- 0.05 Soldering Mask Opening 0.30 mm +/- 0.05 Table 11-2. Device and 217-ball LFBGA Package Maximum Weight 450 mg Table 11-3. 217-ball LFBGA Package Characteristics Moisture Sensitivity Level 3 Table 11-4.
Figure 11-3. 208-lead PQFP: Pin 1 Position One or two ink (or laser) dots may be present on top of the package. Optional, Atmel internal use Only. Figure 11-4.
Table 11-5. Device and 208-lead PQFP Package Maximum Weight 5.5 g Table 11-6. 208-lead PQFP Package Characteristics Moisture Sensitivity Level 3 Table 11-7. Package Reference JEDEC Drawing Reference MS-022 JESD97 Classification e3 11.2 Soldering Profile Table 11-8 gives the recommended soldering profile from J-STD-20. Table 11-8. Soldering Profile Profile Feature PQFP208 Green Package BGA217 Green Package Average Ramp-up Rate (217°C to Peak) 3⋅ C/sec. max. 3⋅ C/sec. max.
12. SAM9260 Ordering Information Table 12-1.
13. Revision History Table 13-1. Revision History - current version appears first Revision Comments Change Req. Ref. 6221LS Removed: 208-pin Package and 217-ball package outlines: Formerly Figure 4-1 and Figure 4-2. Added: Figure 11-1 ”217-ball LFBGA: Ball A1 Position” and Figure 11-3 ”208-lead PQFP: Pin 1 Position”. 8450 Changed document format: pagination has changed.
Table 13-1. Revision History - current version appears first Revision Comments 6221FS All new information in Section 7.2.1 ”Matrix Masters”, Table 7-1, “List of Bus Matrix Masters,” on page 16 and Section 7.2.3 ”Master to Slave Access”, Table 7-3, “SAM9260 Masters to Slaves Access,” on page 16. 4457 In Figure 2-1 ”SAM9260 Block Diagram” on page 3, updated EBI signals NRD, NWR0, NWR1, NWR3. 4431 Added details on Timer/Counter blocks in Section 10.4.5 “Timer Counter” on page 35.
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