Datasheet

91
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
It is made up of:
 A bus arbiter
 An address decoder
 An abort status
 A misalignment detector
 An Embedded Flash Controller
The MC handles only little-endian mode accesses. The masters work in little-endian mode only.
18.3.1 Bus Arbiter
The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the three
masters. The EMAC has the highest priority; the Peripheral DMA Controller has the medium priority; the ARM processor
has the lowest one.
18.3.2 Address Decoder
The Memory Controller features an Address Decoder that first decodes the four highest bits of the 32-bit address bus
and defines three separate areas:
 One 256-Mbyte address space for the internal memories
 One 256-Mbyte address space reserved for the embedded peripherals
 An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if
accessed
Figure 18-2 shows the assignment of the 256-Mbyte memory areas.
Figure 18-2. Memory Areas
18.3.2.1 Internal Memory Mapping
Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address
bits to allocate 1-Mbyte address spaces for the embedded memories.
The allocated memories are accessed all along the 1-Mbyte address space and so are repeated n times within this
address space, n equaling 1M bytes divided by the size of the memory.
When the address of the access is undefined within the internal memory area, the Address Decoder returns an Abort to
the master.
0x0000 0000
0x0FFF FFFF
0x1000 0000
0xEFFF FFFF
0xF000 0000
0xFFFF FFFF
256M Bytes
256M Bytes
14 x 256MBytes
3,584 Mbytes
Internal Memories
Undefined
(Abort)
Peripherals