Datasheet

647
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
Version
6120H Comments
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Ref.
Overview:
Table 3-1, “Signal Description List” footnote added to JTAGSEL, ERASE and TST pin comments.
Section 6.1 ”JTAG Port Pins”, Section 6.2 ”Test Pin” and Section 6.4 ”ERASE Pin”, updated.
5064
Section 8.4.3 ”Internal Flash”, updated: “At any time, the Flash is mapped ... if GPNVM bit 2 is set and before the
Remap Command.”
5850
Figure 9-1,”System Controller Block Diagram”, RTT is reset by power_on_reset. 5223
”Features”, ”Debug Unit (DBGU)”, added ”Mode for General Purpose 2-wire UART Serial Communication” 5846
ADC:
Section 35.6.2 ”ADC Mode Register”, PRESCAL and STARTUP bit fields widened.
“SHTIM: Sample & Hold Time” on page 473 formula updated in bit description.
Figure 35-1,”Analog-to-Digital Converter Block Diagram”, VDDANA replaced by VDDIN. PMC added to figure.
Figure 35.5.5,”Conversion Triggers”, update to the third paragraph detailing hardware trigger.
4430
5254
rfo
AIC:
Section 23.8.16 ”AIC Spurious Interrupt Vector Register”, typo fixed in bit fields. (SIQV is SIVR).
Section 23.7.5 ”Protect Mode”, writing PROT in AIC_DCR enables protection mode (3rd paragraph).
4749
5193
CAN:
Section 36.6.4.6 ”Error Interrupt Handler”, added to datasheet.
Section 36.8.5 ”CAN Status Register”, added references to the new chapter in bit descriptions, WARN, BOFF,
ERRA, ERP.
4736
DBGU:
Section 26.1 ”Overview”, ...” two-pin UART can be used standalone for general purpose serial communication.” 5846
FFPI:
Section 20.2 ”Parallel Fast Flash Programming”, Section 20.2.1 ”Device Configuration”, added status of PIOs
and Crystal Oscillator
Section 20.3 ”Serial Fast Flash Programming”, Section 20.3.1 ”Device Configuration”, added status of PIOs and
Crystal Oscillator
5989
PMC:
”PMC System Clock Enable Register”, ”PMC System Clock Disable Register” and ”PMC System Clock Status
Register”, bit field 11 contains PCK3.
5722
PWM:
Section 33.6.12 ”PWM Channel Counter Register”, typos corrected in bit description. 5185
RSTC:
Section 13.2.4.4 ”Software Reset”, PERRST must be used with PROCRST, except for debug purposes.
SSC:
Section 31.8.3 ”SSC Receive Clock Mode Register”, corrected bit name to STTDLY.