Datasheet

595
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
Figure 38-7. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
Notes: 1. 3.3V domain: V
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 40 pF.
2. t
CPMCK
: Master Clock period in ns.
Note that in SPI master mode the ATSAM7X512/256/128 does not sample the data (MISO) on the opposite edge where
data clocks out (MOSI) but the same edge is used as shown in Figure 38-4 and Figure 38-5.
SPCK
MISO
MOSI
SPI
9
SPI
10
SPI
11
Table 38-21. SPI Timings
Symbol Parameter Conditions Min Max Units
SPI
0
MISO Setup time before SPCK rises (master) 3.3V domain
(1)
28.5 + (t
CPMCK
)/2
(2)
ns
SPI
1
MISO Hold time after SPCK rises (master) 3.3V domain
(1)
0ns
SPI
2
SPCK rising to MOSI Delay (master) 3.3V domain
(1)
2ns
SPI
3
MISO Setup time before SPCK falls (master) 3.3V domain
(1)
26.5 + (t
CPMCK
)/2
(2)
ns
SPI
4
MISO Hold time after SPCK falls (master) 3.3V domain
(1)
0ns
SPI
5
SPCK falling to MOSI Delay (master) 3.3V domain
(1)
2ns
SPI
6
SPCK falling to MISO Delay (slave) 3.3V domain
(1)
28 ns
SPI
7
MOSI Setup time before SPCK rises (slave) 3.3V domain
(1)
2ns
SPI
8
MOSI Hold time after SPCK rises (slave) 3.3V domain
(1)
3ns
SPI
9
SPCK rising to MISO Delay (slave) 3.3V domain
(1)
28 ns
SPI
10
MOSI Setup time before SPCK falls (slave) 3.3V domain
(1)
3ns
SPI
11
MOSI Hold time after SPCK falls (slave) 3.3V domain
(1)
3ns