Datasheet

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SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
11.2.4.1 Modes and Exception Handling
All exceptions have banked registers for R14 and R13.
After an exception, R14 holds the return address for exception processing. This address is used to return after the
exception is processed, as well as to address the instruction that caused the exception.
R13 is banked across exception modes to provide each exception handler with a private stack pointer.
The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these
registers.
A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers.
System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions.
11.2.4.2 Status Registers
All other processor states are held in status registers. The current operating processor status is in the Current Program
Status Register (CPSR). The CPSR holds:
 four ALU flags (Negative, Zero, Carry, and Overflow)
 two interrupt disable bits (one for each type of interrupt)
 one bit to indicate ARM or Thumb execution
 five bits to encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task
immediately preceding the exception.
Table 11-1. ARM7TDMI ARM Modes and Registers Layout
User and
System Mode
Supervisor
Mode Abort Mode
Undefined
Mode
Interrupt
Mode
Fast Interrupt
Mode
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
R8 R8 R8 R8 R8
R8_FIQ
R9 R9 R9 R9 R9
R9_FIQ
R10 R10 R10 R10 R10 R10_FIQ
R11 R11 R11 R11 R11
R11_FIQ
R12 R12 R12 R12 R12
R12_FIQ
R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ
R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ
PC PC PC PC PC PC
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ
Mode-specific banked registers