Datasheet

287

SAM7X Series [DATASHEET]

6120K–ATARM–11-Feb-14

29.6.5 TWI Status Register

Access Type: Read-only

• TXCOMP: Transmission Completed

0 = During the length of the current frame.

1 = When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable TWI).

• RXRDY: Receive Holding Register Ready

0 = No character has been received since the last TWI_RHR read operation.

1 = A byte has been received in the TWI_RHR since the last read.

• TXRDY: Transmit Holding Register Ready

0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.

1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same

time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).

• OVRE: Overrun Error (clear on read)

This bit is only used in Master mode.

0 = TWI_RHR has not been loaded while RXRDY was set

1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.

• NACK: Not Acknowledged

0 = Each data byte has been correctly received by the far-end side TWI slave component.

1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

–––––––NACK

76543210

– OVRE – – – TXRDY RXRDY TXCOMP