Datasheet

277

SAM7X Series [DATASHEET]

6120K–ATARM–11-Feb-14

Figure 29-14. TWI Write Operation with Single Data Byte and Internal Address

BEGIN

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN

Set the Master Mode register:

- Device slave address (DADR)

- Internal address size (IADRSZ)

- Transfer direction bit

Write ==> bit MREAD = 0

Load transmit register

TWI_THR = Data to send

Read Status register

TXRDY = 1?

Read Status register

TXCOMP = 1?

Transfer finished

Set the internal address

TWI_IADR = address

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