Datasheet

136
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decremented.
When the memory block size is reached, a signal is sent to the peripheral and the transfer stops.
The same procedure is followed, in reverse, for transmit transfers.
22.3.5 Priority of PDC Transfer Requests
The Peripheral DMA Controller handles transfer requests from the channel according to priorities fixed for each
product.These priorities are defined in the product datasheet.
If simultaneous requests of the same type (receiver or transmitter) occur on identical peripherals, the priority is
determined by the numbering of the peripherals.
If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are
handled first and then followed by transmitter requests.
22.4 Peripheral DMA Controller (PDC) User Interface
Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the
user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.).
Table 22-1. Register Mapping
Offset
Register Name Access Reset
0x100 Receive Pointer Register PERIPH
(1)
_RPR Read-write 0x0
0x104 Receive Counter Register PERIPH_RCR Read-write 0x0
0x108 Transmit Pointer Register PERIPH_TPR Read-write 0x0
0x10C Transmit Counter Register PERIPH_TCR Read-write 0x0
0x110 Receive Next Pointer Register PERIPH_RNPR Read-write 0x0
0x114 Receive Next Counter Register PERIPH_RNCR Read-write 0x0
0x118 Transmit Next Pointer Register PERIPH_TNPR Read-write 0x0
0x11C Transmit Next Counter Register PERIPH_TNCR Read-write 0x0
0x120 PDC Transfer Control Register PERIPH_PTCR Write-only -
0x124 PDC Transfer Status Register PERIPH_PTSR Read-only 0x0