Datasheet

120
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
The AT91SAM7X512 security bit is controlled by the EFC0. To use the Set Security Bit command, the EFC0 must be
selected using the Select EFC command
Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the Flash.
In order to erase the Flash, the user must perform the following:
 Power-off the chip
 Power-on the chip with TST = 0
 Assert Erase during a period of more than 220 ms
 Power-off the chip
Then it is possible to return to FFPI mode and check that Flash is erased.
20.2.5.7 AT91SAM7X512 Select EFC Command
The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default EFC controller is EFC0.
The Select EFC command (SEFC) allows selection of the current EFC controller.
20.2.5.8 Memory Write Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
Table 20-14. Set Security Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SSE
2 Write handshaking DATA 0
Table 20-15. Select EFC Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SEFC
2 Write handshaking DATA
0 = Select EFC0
1 = Select EFC1
Table 20-16. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WRAM
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking DATA *Memory Address++
5 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handshaking DATA *Memory Address++
n+3 Write handshaking DATA *Memory Address++
... ... ... ...