Datasheet

101
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
Figure 19-2. Code Read Optimization in Thumb Mode for FWS = 0
Note: When FWS is equal to 0, all accesses are performed in a single-cycle access.
Figure 19-3. Code Read Optimization in Thumb Mode for FWS = 1
Note: When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except
for the first one).
Flash Access
Buffer (32 bits)
Master Clock
ARM Request (16-bit)
Code Fetch
Data To ARM
Bytes 0-3 Bytes 4-7
Bytes 0-3
Bytes 0-1
Bytes 2-3 Bytes 4-5 Bytes 6-7
Bytes 8-9 Bytes 10-11 Bytes 12-13
@Byte 0
@Byte 2 @Byte 4
@Byte 6
@Byte 8
@Byte 10 @Byte 12
@Byte 14 @Byte 16
Bytes 14-15
Bytes 4-7
Bytes 8-11
Bytes 8-11
Bytes 12-15 Bytes 16-19
Bytes 12-15
Flash Access
Buffer (32 bits)
Master Clock
ARM Request (16-bit)
Code Fetch
Data To ARM
Bytes 0-3 Bytes 4-7
Bytes 0-3
Bytes 2-3
Bytes 4-5
Bytes 6-7
Bytes 8-9 Bytes 10-11
@Byte 0
@Byte 4
@Byte 6
@Byte 8 @Byte 10
@Byte 12 @Byte 14
Bytes 4-7
Bytes 8-11
Bytes 8-11
Bytes 12-15
1 Wait State Cycle
Bytes 0-1
1 Wait State Cycle 1 Wait State Cycle
1 Wait State Cycle
@Byte 2
Bytes 12-13