ARM-based Flash MCU SAM7X512 / SAM7X256 / SAM7X128 DATASHEET Description The Atmel SAM7X512/256/128 is a highly-integrated Flash microcontroller based on the 32-bit ARM® RISC processor. It features 512/256/128 Kbytes of high-speed Flash and 128/64/32 Kbytes of SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, and a CAN controller. A complete set of system functions minimizes the number of external components.
Features Incorporates the ARM7TDMI ARM Thumb® Processor High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash 512 Kbytes (SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) 256 Kbytes (SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) 128 Kbytes (SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) Single
Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output Thirteen Peripheral DMA Controller (PDC) Channels One USB 2.0 Full Speed (12 Mbits per second) Device Port On-chip Transceiver, 1352-byte Configurable Integrated FIFOs One Ethernet MAC 10/100 base-T Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive One Part 2.0A and Part 2.
1. Configuration Summary of the SAM7X512/256/128 The SAM7X512, SAM7X256 and SAM7X128 differ only in memory sizes. Table 1-1 summarizes the configurations of the three devices. Table 1-1.
SAM7X512/256/128 Block Diagram SAM7X512/256/128 Block Diagram TDI TDO TMS TCK ICE JTAG SCAN ARM7TDMI Processor JTAGSEL 1.
3. Signal Description Table 3-1.
Table 3-1.
Table 3-1. Signal Name ETXER ERXDV ECRSDV ERX0 - ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Note: Signal Description List (Continued) Function Transmit Coding Error Receive Data Valid Carrier Sense and Data Valid Receive Data Receive Error Carrier Sense Collision Detected Management Data Clock Management Data Input/Output Force 100 Mbits/sec.
4. Package The SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS-compliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical description is given in the Mechanical Characteristics section. Figure 4-1. 100-lead LQFP Package Outline (Top View) 75 51 76 50 100 26 1 4.2 25 100-lead LQFP Pinout Table 4-1.
4.3 100-ball TFBGA Package Outline Figure 4-2 shows the orientation of the 100-ball TFBGA package. A detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-2. 100-ball TFBGA Package Outline (Top View) TOP VIEW 10 9 8 7 6 5 4 3 2 1 BALL A1 4.
5. Power Considerations 5.1 Power Supplies The SAM7X512/256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal. In order to decrease current consumption, if the voltage regulator and the ADC are not used, VDDIN, ADVREF, AD4, AD5, AD6 and AD7 should be connected to GND.
Figure 5-1. 3.3V System Single Power Supply Schematic VDDFLASH Power Source ranges from 4.5V (USB) to 18V DC/DC Converter VDDIO VDDIN Voltage Regulator 3.
6. I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND.
6.6 I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA.
7. Processor and Architecture 7.1 ARM7TDMI Processor RISC processor based on ARMv4T Von Neumann architecture 7.2 Two instruction sets ARM high-performance 32-bit instruction set Thumb high code density 16-bit instruction set Three-stage pipeline architecture Instruction Fetch (F) Instruction Decode (D) Execute (E) Debug and Test Features 7.3 Runs at up to 55 MHz, providing 0.
7.
8. Memories 8.
Figure 8-1.
8.4 Memory Mapping 8.4.1 Internal SRAM The SAM7X512 embeds a high-speed 128-Kbyte SRAM bank. The SAM7X256 embeds a high-speed 64-Kbyte SRAM bank. The SAM7X128 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.4.2 Internal ROM The SAM7X512/256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000.
Figure 8-3. Internal Memory Mapping with GPNVM Bit 2 = 1 0x0000 0000 0x000F FFFF Flash Before Remap SRAM After Remap 1 M Bytes 0x0010 0000 Internal FLASH 1 M Bytes Internal SRAM 1 M Bytes Internal ROM 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 0x003F FFFF 0x0040 0000 252 M Bytes Undefined Areas (Abort) 0x0FFF FFFF 8.5 Embedded Flash 8.5.1 Flash Overview The Flash of the SAM7X512 is organized in two banks (dual plane) of 1024 pages of 256 bytes.
8.5.3 8.5.3.1 Lock Regions SAM7X512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The SAM7X512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 32 NVM bits are software programmable through both of the EFC User Interfaces.
8.5.6 The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default. Calibration Bits Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
9. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 9-1 on page 24 shows the System Controller Block Diagram. Figure 8-1 on page 18 shows the mapping of the User Interface of the System Controller peripherals.
Figure 9-1. System Controller Block Diagram System Controller Boundary Scan TAP Controller jtag_nreset nirq irq0-irq1 Advanced Interrupt Controller fiq periph_irq[2..
9.1 9.1.1 Reset Controller Based on one power-on reset cell and one brownout detector Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset Controls the internal resets and the NRST pin output Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. Brownout Detector and Power-on Reset The SAM7X512/256/128 embeds one brownout detection circuit and a power-on reset cell.
9.2 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: RC Oscillator ranges between 22 KHz and 42 KHz Main Oscillator frequency ranges between 3 and 20 MHz Main Oscillator can be bypassed PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2.
9.3 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: the Processor Clock PCK the Master Clock MCK the USB Clock UDPCK all the peripheral clocks, independently controllable four programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device.
Protect Mode Fast Forcing Comprises: One two-pin UART One Interface for the Debug Communication Channel (DCC) support One set of Chip ID Registers One Interface providing ICE Access Prevention Two-pin UART USART-compatible User Interface Programmable Baud Rate Generator Parity, Framing and Overrun Error Automatic Echo, Local Loopback and Remote Loopback Channel Modes Debug Communication Channel Support 9.8 9.
9.10 Half a clock period glitch filter Multi-drive option enables driving in open drain Programmable pull-up on each I/O line Pin data status register, supplies visibility of the level on the pin at any time Synchronous output, provides Set and Clear of several I/O lines in a single write Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).
10. Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 Mbytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in Figure 8-1 on page 18. 10.2 Peripheral Identifiers The SAM7X512/256/128 embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the SAM7X512/256/128.
10.3 Peripheral Multiplexing on PIO Lines The SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller.
10.4 PIO Controller A Multiplexing Table 10-2.
10.5 PIO Controller B Multiplexing Table 10-3.
10.6 10.7 Ethernet MAC DMA Master on Receive and Transmit Channels Compatible with IEEE Standard 802.
10.9 USART Programmable Baud Rate Generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications 1, 1.
Five internal clock inputs, as defined in Table 10-4 Table 10-4. Timer Counter Clocks Assignment TC Clock input Clock TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 MCK/1024 Two multi-purpose input/output signals Two global registers that act on all three TC channels 10.
16-bit internal timer for time stamping and network synchronization Programmable reception buffer length up to 8 mailbox objects Priority management between transmission mailboxes Autobaud and listening mode Low power mode and programmable wake-up on bus activity or by the application Data, remote, error and overload frame handling 10.15 Analog-to-Digital Converter 8-channel ADC 10-bit 384 K samples/sec.
11. ARM7TDMI Processor Overview 11.1 Overview The ARM7TDMI core executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages.
11.2 ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) 11.2.1 Instruction Type Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). 11.2.2 Data Type ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries.
Table 11-1.
11.2.4.3 Exception Types The ARM7TDMI supports five types of exception and a privileged processing mode for each type. The types of exceptions are: fast interrupt (FIQ) normal interrupt (IRQ) memory aborts (used to implement memory protection or virtual memory) attempted execution of an undefined instruction software interrupts (SWIs) Exceptions are generated by internal and external sources. More than one exception can occur in the same time.
Table 11-2.
Table 11-3.
12. Debug and Test Features 12.1 Description The SAM7X Series features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM.
12.3 Application Examples 12.3.1 Debug Environment Figure 12-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2.
12.3.2 Test Environment Figure 12-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n AT91SAM7Xxx Chip 2 Chip 1 AT91SAM7Xxx-based Application Board In Test 12.
12.5.2 EmbeddedICE (Embedded In-circuit Emulator) The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port. The internal state of the ARM7TDMI is examined through an ICE/JTAG port. The ARM7TDMI processor contains hardware extensions for advanced debugging features: In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system.
Each SAM7X input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 12-2.
Table 12-2.
Table 12-2.
Table 12-2.
Table 12-2.
Table 12-2.
12.5.5 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number AT91SAM7X512: 0x5B18 AT91SAM7X256: 0x5B17 AT91SAM7X128: 0x5B16 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1.
13. Reset Controller (RSTC) The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. A brownout detection is also available to prevent the processor from falling into an unpredictable state. 13.1 Block Diagram Figure 13-1.
13.2 Functional Description 13.2.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: proc_nreset: Processor reset line. It also resets the Watchdog Timer. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. 13.2.3 Brownout Manager Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal.
13.2.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 13.2.4.1 Power-up Reset When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock.
13.2.4.2 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup.
13.2.4.3 Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered.
13.2.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
13.2.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.
13.2.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: Power-up Reset Brownout Reset Watchdog Reset Software Reset User Reset Particular cases are listed below: When in User Reset: A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. A software reset is impossible, since the processor reset is being activated.
13.2.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: RSTTYP field: This field gives the type of the last reset, as explained in previous sections. SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
13.3 Reset Controller (RSTC) User Interface Table 13-1.
13.3.1 Reset Controller Control Register Register Name: RSTC_CR Access Type: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect.
13.3.2 Reset Controller Status Register Register Name: RSTC_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 BODSTS 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
13.3.3 Reset Controller Mode Register Register Name: RSTC_MR Access Type: Read-write 31 30 29 28 27 26 25 24 17 – 16 BODIEN 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.
14. Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value. 14.2 Block Diagram Figure 14-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK RTTINCIEN reload 16-bit Divider set 0 RTT_MR RTTRST RTT_SR 1 RTTINC reset 0 rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR reset CRTV RTT_SR ALMS set rtt_alarm = RTT_AR 14.
The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented.
14.4 Real-time Timer (RTT) User Interface Table 14-1.
14.4.1 Real-time Timer Mode Register Register Name: RTT_MR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer.
14.4.2 Real-time Timer Alarm Register Register Name: RTT_AR Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 14.4.
14.4.4 Real-time Timer Status Register Register Name: RTT_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.
15. Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1.
15.3 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
15.4 Periodic Interval Timer (PIT) User Interface Table 15-1.
15.4.1 Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 14 13 12 25 PITIEN 24 PITEN 17 16 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
15.4.2 Periodic Interval Timer Status Register Register Name: PIT_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
15.4.3 Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
15.4.4 Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
16. Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.2 Block Diagram Figure 16-1.
16.3 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
Figure 16-2.
16.4 Watchdog Timer (WDT) User Interface Table 16-1. Register Mapping Offset Register Name Access Reset Value 0x00 Control Register WDT_CR Write-only - 0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000 16.4.
16.4.2 Watchdog Timer Mode Register Register Name: WDT_MR Access Type: Read-write Once 31 – 30 – 29 WDIDLEHLT 28 WDDBGHLT 27 26 23 22 21 20 19 18 11 10 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
16.4.3 Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
17. Voltage Regulator Mode Controller (VREG) 17.1 Overview The Voltage Regulator Mode Controller contains one Read-write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake up the Voltage Regulator in Normal Mode.
17.2 Voltage Regulator Power Controller (VREG) User Interface Table 17-1. Register Mapping Offset Register Name 0x60 Voltage Regulator Mode Register VREG_MR Access Reset Value Read-write 0x0 17.2.
18. Memory Controller (MC) 18.1 Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a bus arbiter, an address decoder, an abort status, a misalignment detector and an Embedded Flash Controller. 18.2 Block Diagram Figure 18-1.
It is made up of: A bus arbiter An address decoder An abort status A misalignment detector An Embedded Flash Controller The MC handles only little-endian mode accesses. The masters work in little-endian mode only. 18.3.1 Bus Arbiter The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the three masters. The EMAC has the highest priority; the Peripheral DMA Controller has the medium priority; the ARM processor has the lowest one.
Figure 18-3. Internal Memory Mapping 0x0000 0000 Internal Memory Area 0 1 M Bytes 0x000F FFFF 0x0010 0000 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 0x003F FFFF 0x0040 0000 Internal Memory Area 1 Internal Flash 1 M Bytes Internal Memory Area 2 Internal SRAM 1 M Bytes Internal Memory Area 3 Internal ROM 1 M Bytes Undefined Areas (Abort) 252 M Bytes 0x0FFF FFFF 18.3.2.
the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP) whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned address (bit MISADD) the source of the access leading to the last abort (bits MST_EMAC, MST_PDC and MST_ARM) whether or not an abort occurred for each master since the last read of the register (bits SVMST_EMAC, SVMST_PDC and SVMST_ARM) unless this information is loaded in MST bits In the case of a Data Abort from
18.4 Memory Controller (MC) User Interface Base Address: 0xFFFFFF00 Table 18-1. Register Mapping Offset Register Name Access 0x00 MC Remap Control Register MC_RCR Write-only 0x04 MC Abort Status Register MC_ASR Read-only 0x0 0x08 MC Abort Address Status Register MC_AASR Read-only 0x0 0x10-0x5C Reserved 0x60 EFC0 Configuration Registers 0x70 EFC1(1) Configuration Registers Note: Reset State See the Embedded Flash Controller Section 1. EFC1 pertains to AT91SAM7X512 only.
18.4.1 MC Remap Control Register Register Name: MC_RCR Access Type: Write-only Offset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – RCB • RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices.
18.4.
• MST_PDC: PDC Abort Source 0: The last aborted access was not due to the PDC. 1: The last aborted access was due to the PDC. • MST_ARM: ARM Abort Source 0: The last aborted access was not due to the ARM. 1: The last aborted access was due to the ARM. • SVMST_EMAC: Saved EMAC Abort Source 0: No abort due to the EMAC occurred since the last read of MC_ASR or it is notified in the bit MST_EMAC. 1: At least one abort due to the EMAC occurred since the last read of MC_ASR.
18.4.3 MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Offset: 0x08 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ABTADD 23 22 21 20 ABTADD 15 14 13 12 ABTADD 7 6 5 4 ABTADD • ABTADD: Abort Address This field contains the address of the last aborted access.
19. Embedded Flash Controller (EFC) 19.1 Overview The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the interface of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands. The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the Security bit and GPNVM bits.
Figure 19-1. Embedded Flash Memory Mapping Page 0 Flash Memory Start Address Lock Region 0 Lock Bit 0 Lock Region 1 Lock Bit 1 Lock Region (n-1) Lock Bit n-1 Page (m-1) Page ( (n-1)*m ) 32-bit wide Page (n*m-1) 19.2.2 Read Operations An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added in order to start access at following address during the second read, thus increasing performance when the processor is running in Thumb mode (16-bit instruction set).
Figure 19-2.
Figure 19-4.
All the commands are protected by the same keyword, which has to be written in the eight highest bits of the MC_FCR register. Writing MC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the memory plane; however, the PROGE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register.
The Flash technology requires that an erase must be done before programming. The entire memory plane can be erased at the same time, or a page can be automatically erased by clearing the NEBP bit in the MC_FMR register before writing the command in the MC_FCR register. By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps if it has been erased before (see Figure 19-6). Figure 19-6.
When programming is complete, the bit FRDY bit in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Two errors can be detected in the MC_FSR register after a programming sequence: 19.2.4.3 Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register. Lock Error: At least one lock region to be erased is protected.
If the general-purpose bit number is greater than the total number of general-purpose bits, then the command has no effect. It is possible to deactivate a general-purpose NVM bit set previously. The clear sequence is: Start the Clear General-purpose Bit command (CGPB) by writing the Flash Command Register with CGPB and the number of the general-purpose bit to be cleared in the PAGEN field. When the clear completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises.
19.3 Embedded Flash Controller (EFC ) User Interface The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1, as described in the Register Mapping tables and Register descriptions that follow. Table 19-3.
19.3.1 MC Flash Mode Register Register Name: MC_FMR Access Type: Read-write Offset: (EFC0) 0x60 Offset: (EFC1) 0x70 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 FMCN 15 – 14 – 13 – 12 – 11 – 10 – 9 7 NEBP 6 – 5 – 4 – 3 PROGE 2 LOCKE 1 – 8 FWS 0 FRDY • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready generates an interrupt.
• FMCN: Flash Microsecond Cycle Number Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the number of Master Clock cycles in one microsecond. When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up. Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds.
19.3.2 MC Flash Command Register Register Name: MC_FCR Access Type: Write-only Offset: (EFC0) 0x64 Offset: (EFC1) 0x74 31 30 29 28 27 26 25 24 19 – 18 – 17 11 10 9 8 3 2 1 0 KEY 23 – 22 – 21 – 20 – 15 14 13 12 16 PAGEN PAGEN 7 – 6 – 5 – 4 – FCMD • FCMD: Flash Command This field defines the Flash commands: FCMD 0000 0001 0010 Operations No command. Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR.
• PAGEN: Page Number Command PAGEN Description Write Page Command PAGEN defines the page number to be written. Write Page and Lock Command PAGEN defines the page number to be written and its associated lock region. Erase All Command This field is meaningless Set/Clear Lock Bit Command PAGEN defines one page number of the lock region to be locked or unlocked. Set/Clear General Purpose NVM Bit Command PAGEN defines the general-purpose bit number.
19.3.
20. Fast Flash Programming Interface (FFPI) 20.1 Overview The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. The serial interface uses the standard IEEE 1149.1 JTAG protocol.
Table 20-1. Signal Description List (Continued) Signal Name Function Type VDDPLL PLL Power Supply Power GND Ground Ground Active Level Comments Clocks Main Clock Input. This input can be tied to GND. In this case, the device is clocked by the internal RC oscillator.
Table 20-3.
Figure 20-2. Parallel Programming Timing, Write Sequence NCMD 2 4 3 RDY 5 NOE NVALID DATA[15:0] 1 MODE[3:0] Table 20-4.
Table 20-5. Read Handshake Step Programmer Action Device Action DATA I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latch MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Sets DATA signal in tristate Waits for NOE Low Input 5 Clears NOE signal 6 Waits for NVALID low Tristate 7 Sets DATA bus in output mode and outputs the flash contents.
20.2.5.2 Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash: before access to any page other than the current one when a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes.
In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are also cleared by the EA command. Table 20-10. Set and Clear Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE SLB or CLB 2 Write handshaking DATA Bit Mask Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set.. Table 20-11.
The AT91SAM7X512 security bit is controlled by the EFC0. To use the Set Security Bit command, the EFC0 must be selected using the Select EFC command Table 20-14. Set Security Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE SSE 2 Write handshaking DATA 0 Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the Flash.
20.2.5.9 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-17.
20.3 Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and BoundaryScan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a description of the TAP controller states. In this mode, data read/written from/to the embedded Flash of the device are transmitted through the JTAG interface of the device. 20.3.
Table 20-18. Signal Description List (Continued) Signal Name Function Type Active Level Comments Test TST Test Mode Select Input High Must be connected to VDDIO.
address field and 1 to the read/write bit. A register is read by scanning its address into the address field and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data. Refer to the ARM7TDMI reference manuel for more information on Comm channel operations. Figure 20-5.
Table 20-20. 20.3.4.2 Read Command (Continued) Read/Write DR Data Read Memory [address+4] ... ... Read Memory [address+(Number of Words to Read - 1)* 4] Flash Write Command This command is used to write the Flash contents. The address transmitted must be a valid Flash address in the memory plane. The Flash memory plane is organized into several pages. Data to be written is stored in a load buffer that corresponds to a Flash memory page.
In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits can also be cleared by the EA command. Table 20-23. Set and Clear Lock Bit Command Read/Write DR Data Write SLB or CLB Write Bit Mask Lock bits can be read using Get Lock Bit command (GLB). When a bit set in the Bit Mask is returned, then the corresponding lock bit is active. Table 20-24. 20.3.4.
Assert Erase during a period of more than 220 ms Power-off the chip Then it is possible to return to FFPI mode and check that Flash is erased. 20.3.4.7 AT91SAM7X512 Select EFC Command The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default EFC controller is EFC0. The Select EFC command (SEFC) allows selection of the current EFC controller. Table 20-28. 20.3.4.
21. AT91SAM Boot Program 21.1 Overview The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. SAM-BA Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port. 21.2 Flow Diagram The Boot Program implements the algorithm in Figure 21-1. Figure 21-1.
21.4 SAM-BA Boot The SAM-BA boot principle is to: Check if USB Device enumeration has occurred Check if the AutoBaudrate sequence has succeeded (see Figure 21-2) Figure 21-2. AutoBaudrate Flow Diagram Device Setup Character '0x80' received ? No 1st measurement Yes Character '0x80' received ? No 2nd measurement No Test Communication Yes Character '#' received ? Yes UART operational Send Character '>' Run SAM-BA Boot Table 21-1.
Note: Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. Address: Address in hexadecimal. Value: Byte, halfword or word to write in hexadecimal. Output: ‘>’. Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. Address: Address in hexadecimal Output: The byte, halfword or word read in hexadecimal following by ‘>’ Send a file (S): Send a file to a specified address Address: Address in hexadecimal Output: ‘>’.
Figure 21-3. Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 21.4.3 USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB.
The device also handles some class requests defined in the CDC class. Table 21-3. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 21.4.3.
21.5 Hardware and Software Constraints SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available size for the user code is 122880 bytes for SAM7x512, 57344 bytes for SAM7X256 and 24576 bytes for SAM7X128. USB requirements: pull-up on DDP 18.432 MHz Quartz Table 21-4.
22. Peripheral DMA Controller (PDC) 22.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor intervention and removes the processor interrupt-handling overhead.
The size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel. The memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. It is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers.
After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decremented. When the memory block size is reached, a signal is sent to the peripheral and the transfer stops. The same procedure is followed, in reverse, for transmit transfers. 22.3.5 Priority of PDC Transfer Requests The Peripheral DMA Controller handles transfer requests from the channel according to priorities fixed for each product.These priorities are defined in the product datasheet.
22.4.1 PDC Receive Pointer Register Register Name: PERIPH_RPR Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Address Address of the next receive transfer. 22.4.
22.4.3 PDC Transmit Pointer Register Register Name: PERIPH_TPR Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Pointer Address Address of the transmit buffer. 22.4.
22.4.5 PDC Receive Next Pointer Register Register Name: PERIPH_RNPR Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when the current buffer is full. 22.4.
22.4.7 PDC Transmit Next Pointer Register Register Name: PERIPH_TNPR Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer is empty. 22.4.
22.4.9 PDC Transfer Control Register Register Name: PERIPH_PTCR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXTDIS TXTEN 7 6 5 4 3 2 1 0 – – – – – – RXTDIS RXTEN • RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables the receiver PDC transfer requests if RXTDIS is not set. • RXTDIS: Receiver Transfer Disable 0 = No effect.
22.4.10 PDC Transfer Status Register Register Name: PERIPH_PTSR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – TXTEN 7 6 5 4 3 2 1 0 – – – – – – – RXTEN • RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. 1 = Receiver PDC transfer requests are enabled.
23. Advanced Interrupt Controller (AIC) 23.1 Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
23.3 Application Block Diagram Figure 23-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 23.4 AIC Detailed Block Diagram Figure 23-3.
23.6 Product Dependencies 23.6.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path. 23.6.2 Power Management The Advanced Interrupt Controller is continuously clocked.
23.7 Functional Description 23.7.1 Interrupt Source Control 23.7.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode.
23.7.1.5 Internal Interrupt Source Input Stage Figure 23-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Edge AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR 23.7.1.6 External Interrupt Source Input Stage Figure 23-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg.
23.7.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: The time the software masks the interrupts. Occurrence, either at the processor level or at the AIC level. The execution time of the instruction in progress when the interrupt occurs. The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations.
23.7.2.3 Internal Interrupt Edge Triggered Source Figure 23-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active 23.7.2.4 Internal Interrupt Level Sensitive Source Figure 23-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 23.7.3 Normal Interrupt 23.7.3.
23.7.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is reasserted.
Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. Automatically clears the interrupt, if it has been programmed to be edge-triggered. Pushes the current level and the current interrupt number on to the stack.
23.7.4 Fast Interrupt 23.7.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. 23.7.4.2 Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller.
6. Note: Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR. The “F” bit in SPSR is significant.
Figure 23-10. Fast Forcing Source 0 _ FIQ AIC_IPR Input Stage Automatic Clear AIC_IMR nFIQ Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR Source n AIC_IPR Input Stage Priority Manager Automatic Clear AIC_IMR nIRQ Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n.
23.7.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR.
23.7.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode.
23.8 Advanced Interrupt Controller (AIC) User Interface 23.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only an ± 4-Kbyte offset. 23.8.2 Register Mapping Table 23-2.
23.8.3 AIC Source Mode Register Register Name: AIC_SMR0..AIC_SMR31 Access Type: Read-write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – SRCTYPE PRIOR • PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest).
23.8.4 AIC Source Vector Register Register Name: AIC_SVR0..AIC_SVR31 Access Type: Read-write Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. 23.8.
23.8.6 AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Read-only Reset Value: 0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. 23.8.
23.8.
23.8.10 AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read-only Reset Value: 0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NIFQ • NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active. 23.8.
23.8.12 AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect.
23.8.14 AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt.
23.8.16 AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type: Read-write Reset Value: 0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. 23.8.
23.8.18 AIC Fast Forcing Enable Register Register Name: AIC_FFER Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Enable 0 = No effect.
23.8.
24. Clock Generator 24.1 Overview The Clock Generator is made up of 1 PLL, a Main Oscillator, as well as an RC Oscillator . It provides the following clocks: SLCK, the Slow Clock, which is the only permanent clock within the system MAINCK is the output of the Main Oscillator PLLCK is the output of the Divider and PLL block The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 25.9.
Figure 24-2. Typical Crystal Connection AT91SAM7X Microcontroller XIN XOUT GND 1K 24.3.2 Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the frequency rises. 24.3.3 Main Oscillator Control To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected.
24.4 Divider and PLL Block The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLL minimum input frequency when programming the divider. Figure 24-3 shows the block diagram of the divider and PLL block. Figure 24-3. Divider and PLL Block Diagram DIV MUL Divider MAINCK OUT PLLCK PLL PLLRC PLLCOUNT PLL Counter SLCK LOCK 24.4.1 PLL Filter The PLL requires connection to an external second-order filter through the PLLRC pin.
time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel.
25. Power Management Controller (PMC) 25.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks: 25.2 MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device.
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 25.
Moreover, like the PCK, a status bitin PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed. 25.7 Programming Sequence 1.
write_register(CKGR_PLLR,0x00040805) If PLL and divider are enabled, the PLL input clock is the main clock. PLL output clock is PLL input clock multiplied by 5. Once CKGR_PLLR has been written, LOCK bit will be set after eight slow clock cycles. 4. Selection of Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR register. The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow clock.
Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 4 Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled. PMC_PCKx registers are used to configure Programmable clocks. The CSS field is used to select the Programmable clock divider source. Four clock options are available: main clock, slow clock, PLLCK.
25.8 Clock Switching Details 25.8.1 Master Clock Switching Timings Table 25-1 gives the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 25-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock – 4 x SLCK + 2.5 x Main Clock 0.5 x Main Clock + 4.
Figure 25-4. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR Figure 25-5.
Figure 25-6.
25.9 Power Management Controller (PMC) User Interface Table 25-2.
25.9.1 PMC System Clock Enable Register Register Name: PMC_SCER Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP – – – – – – – • UDP: USB Device Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock of the USB Device Port. • PCKx: Programmable Clock x Output Enable 0 = No effect.
25.9.2 PMC System Clock Disable Register Register Name: PMC_SCDR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP – – – – – – PCK • PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode. • UDP: USB Device Port Clock Disable 0 = No effect.
25.9.3 PMC System Clock Status Register Register Name: PMC_SCSR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP – – – – – – PCK • PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled.
25.9.4 PMC Peripheral Clock Enable Register Register Name: PMC_PCER Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0 = No effect.
25.9.6 PMC Peripheral Clock Status Register Register Name: PMC_PCSR Access Type: Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 – – • PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled.
25.9.7 PMC Clock Generator Main Oscillator Register Register Name: CKGR_MOR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 OSCBYPASS 0 MOSCEN OSCOUNT 7 – 6 – 5 – 4 – • MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Oscillator is disabled. 1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0.
25.9.8 PMC Clock Generator Main Clock Frequency Register Register Name: CKGR_MCFR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled.
25.9.9 PMC Clock Generator PLL Register Register Name: CKGR_PLLR Access Type: Read-write 31 – 30 – 29 23 22 21 28 USBDIV 20 27 – 26 25 MUL 24 19 18 17 16 10 9 8 2 1 0 MUL 15 14 13 12 11 OUT 7 PLLCOUNT 6 5 4 3 DIV Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. • DIV: Divider DIV Divider Selected 0 Divider output is 0 1 Divider is bypassed 2 - 255 Divider output is the selected clock divided by DIV.
25.9.10 PMC Master Clock Register Register Name: PMC_MCKR Access Type: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 4 3 2 1 7 6 5 – – – PRES 0 CSS • CSS: Master Clock Selection CSS Clock Source Selection 0 0 Slow Clock is selected 0 1 Main Clock is selected 1 0 Reserved 1 1 PLL Clock is selected.
25.9.
25.9.
25.9.
25.9.14 PMC Status Register Register Name: PMC_SR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 – – – – MCKRDY LOCK – MOSCS • MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized. • LOCK: PLL Lock Status 0 = PLL is not locked 1 = PLL is locked.
25.9.
26. Debug Unit (DBGU) 26.1 Overview The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARMbased systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used standalone for general purpose serial communication.
26.2 Block Diagram Figure 26-1. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB Debug Unit DTXD Transmit Power Management Controller Parallel Input/ Output Baud Rate Generator MCK Receive DRXD COMMRX DCC Handler R ARM Processor COMMTX Chip ID nTRST ICE Access Handler Interrupt Control dbgu_irq Power-on Reset force_ntrst Table 26-1.
26.3 Product Dependencies 26.3.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. 26.3.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock.
26.4.2 Receiver 26.4.2.1 Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped.
Figure 26-6. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 S P D0 D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 26.4.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 26-7.
26.4.3 Transmitter 26.4.3.1 Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1.
Figure 26-11. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register DTXD Data 0 S Data 0 Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 26.4.4 Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel.
Figure 26-12. Test Modes Automatic Echo RXD Receiver Disabled Transmitter TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback TXD VDD Disabled Receiver Transmitter Disabled RXD TXD 26.4.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size ARCH - identifies the set of embedded peripheral SRAMSIZ - indicates the size of the embedded SRAM EPROC - indicates the embedded ARM processor VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 26.4.8 ICE Access Prevention The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface.
26.5 Debug Unit (DBGU) User Interface Table 26-2.
26.5.1 Debug Unit Control Register Name: DBGU_CR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. • RSTTX: Reset Transmitter 0 = No effect.
26.5.
26.5.
26.5.
26.5.
26.5.6 Debug Unit Status Register Name: DBGU_SR Access Type: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active.
26.5.7 Debug Unit Receiver Holding Register Name: DBGU_RHR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
26.5.8 Debug Unit Transmit Holding Register Name: DBGU_THR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
26.5.
26.5.
• NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 Size 0 0 0 0 None 0 0 0 1 8K bytes 0 0 1 0 16K bytes 0 0 1 1 32K bytes 0 1 0 0 Reserved 0 1 0 1 64K bytes 0 1 1 0 Reserved 0 1 1 1 128K bytes 1 0 0 0 Reserved 1 0 0 1 256K bytes 1 0 1 0 512K bytes 1 0 1 1 Reserved 1 1 0 0 1024K bytes 1 1 0 1 Reserved 1 1 1 0 2048K bytes 1 1 1 1 Reserved • SRAMSIZ: Internal SRAM Size SRAMSIZ Size 0 0 0 0 Reserved 0 0 0 1 1K byt
• ARCH: Architecture Identifier ARCH Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x37 0011 0111 CAP7 Series 0x39 0011 1001 CAP9 Series 0x3B 0011 1011 CAP11 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0110 0000 AT91SAM7Axx Series 0x61 0110 0001 AT91SAM7AQxx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 011
26.5.11 Debug Unit Chip ID Extension Register Name: DBGU_EXID Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. 26.5.
27. Parallel Input/Output Controller (PIO) 27.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
Figure 27-2. Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver 27.3 General Purpose I/Os External Devices Product Dependencies 27.3.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os.
27.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 27-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 27-3.
results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0. 27.4.
27.4.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are written.
Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge.
Figure 27-6.
27.5 I/O Lines Programming Example The programing example as shown in Table 27-1 below is used to define the following configuration.
27.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 27-2.
Table 27-2.
27.6.1 PIO Controller PIO Enable Register Name: PIO_PER Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 27.6.
27.6.3 PIO Controller PIO Status Register Name: PIO_PSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active).
27.6.5 PIO Controller Output Disable Register Name: PIO_ODR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line. 27.6.
27.6.7 PIO Controller Input Filter Enable Register Name: PIO_IFER Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. 27.6.
27.6.9 PIO Controller Input Filter Status Register Name: PIO_IFSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. 27.6.
27.6.11 PIO Controller Clear Output Data Register Name: PIO_CODR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 27.6.
27.6.13 PIO Controller Pin Data Status Register Name: PIO_PDSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. 27.6.
27.6.15 PIO Controller Interrupt Disable Register Name: PIO_IDR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. 27.6.
27.6.17 PIO Controller Interrupt Status Register Name: PIO_ISR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
27.6.19 PIO Multi-driver Disable Register Name: PIO_MDDR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line. 27.6.
27.6.21 PIO Pull Up Disable Register Name: PIO_PUDR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line. 27.6.
27.6.23 PIO Pull Up Status Register Name: PIO_PUSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. 27.6.
27.6.25 PIO Peripheral B Select Register Name: PIO_BSR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function. 27.6.
27.6.27 PIO Output Write Enable Register Name: PIO_OWER Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. 27.6.
27.6.29 PIO Output Write Status Register Name: PIO_OWSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line.
28. Serial Peripheral Interface (SPI) 28.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
28.3 Application Block Diagram Figure 28-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 NC NPCS3 MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 28.4 Signal Description Table 28-1.
28.5 Product Dependencies 28.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. 28.5.2 Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. 28.5.
28.6 Functional Description 28.6.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode.
Figure 28-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 28-4.
28.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
28.6.3.1 Master Mode Block Diagram Figure 28-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
28.6.3.2 Master Mode Flow Diagram Figure 28-6. Master Mode Flow Diagram S SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
28.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to.
Figure 28-8. Peripheral Deselection CSAAT = 0 TDRE NPCS[0..3] CSAAT = 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B A B DLYBCS PCS = B DLYBCS PCS = B Write SPI_TDR 28.6.3.8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal.
SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0.
28.7 Serial Peripheral Interface (SPI) User Interface Table 28-3.
28.7.1 SPI Control Register Name: SPI_CR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer.
28.7.2 SPI Mode Register Name: SPI_MR Access Type: Read-write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 3 7 6 5 4 LLB – – MODFDIS PCS 2 1 0 PCSDEC PS MSTR • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.
PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times.
28.7.3 SPI Receive Data Register Name: SPI_RDR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer.
28.7.4 SPI Transmit Data Register Name: SPI_TDR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
28.7.
1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. • SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. Note: 1.
28.7.
28.7.
28.7.
28.7.9 SPI Chip Select Register Name: SPI_CSR0... SPI_CSR3 Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 3 2 1 0 CSAAT – NCPHA CPOL • CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK).
BITS 1101 1110 1111 Bits Per Transfer Reserved Reserved Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCK SPCK Baudrate = --------------SCBR Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
29. Two-wire Interface (TWI) 29.1 Overview The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
29.3 Application Block Diagram Figure 29-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 29.3.1 I/O Lines Description Table 29-2. 29.4 I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output Product Dependencies 29.4.
29.5 Functional Description 29.5.1 Transfer format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 29-4 on page 271). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 29-3 on page 271). A high-to-low transition on the TWD line while TWCK is high defines the START condition.
Figure 29-5. Master Write with One Data Byte TWD S DADR W A DATA A P TXCOMP TXRDY STOP sent automaticaly (ACK received and TXRDY = 1) Write THR (DATA) Figure 29-6. Master Write with Multiple Data Byte S TWD DADR W A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Figure 29-7.
29.5.4 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge.
29.5.5 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 29.5.5.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
1. Program IADRSZ = 1, 2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.) 3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 29-12 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 29-12.
29.5.6 Read/Write Flowcharts The following flowcharts shown in Figure 29-13, Figure 29-14 on page 277, Figure 29-15 on page 278, Figure 29-16 on page 279, Figure 29-17 on page 280 and Figure 29-18 on page 281 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 29-13.
Figure 29-14.
Figure 29-15.
Figure 29-16.
Figure 29-17.
Figure 29-18.
29.6 TWI User Interface Table 29-3.
29.6.1 TWI Control Register Register Name: TWI_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
29.6.2 TWI Master Mode Register Register Name: TWI_MMR Address Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 DADR 18 17 16 15 – 14 – 13 – 12 MREAD 11 – 10 – 9 7 – 6 – 5 – 4 – 3 – 2 – 1 – 8 IADRSZ 0 – • IADRSZ: Internal Device Address Size Table 29-4.
29.6.3 TWI Internal Address Register Register Name: TWI_IADR Access Type: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. – Low significant byte address in 10-bit mode addresses.
29.6.
29.6.5 TWI Status Register Register Name: TWI_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 OVRE 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed 0 = During the length of the current frame. 1 = When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable TWI).
29.6.6 TWI Interrupt Enable Register Register Name: TWI_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 OVRE 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready OVRE: Overrun Error Interrupt Enable • NACK: Not Acknowledge 0 = No effect.
29.6.8 TWI Interrupt Mask Register Register Name: TWI_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 – 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • OVRE: Overrun Error Interrupt Mask • NACK: Not Acknowledge 0 = The corresponding interrupt is disabled.
29.6.
30. Universal Synchronous Asynchronous Receiver Transceiver (USART) 30.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
30.2 Block Diagram Figure 30-1.
30.3 Application Block Diagram Figure 30-2. Application Block Diagram IrLAP PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrDA Driver USART RS232 Drivers RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers Modem PSTN 30.4 I/O Lines Description Table 30-1.
30.5 Product Dependencies 30.5.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
30.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: 5- to 9-bit full-duplex asynchronous serial communication MSB- or LSB-first 1, 1.
Figure 30-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD SCK 0 1 16-bit Counter 2 FIDI >1 3 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 30.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
Table 30-2. Baud Rate Example (OVER = 0) (Continued) Source Clock Expected Baud Rate Calculation Result CD Actual Baud Rate Error 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.
Figure 30-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 16-bit Counter 2 glitch-free logic 3 FIDI >1 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 30.6.1.4 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR.
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 30-4. Table 30-4. Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 30-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 30-5.
The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset.
Figure 30-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 30.6.3.2 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line.
Figure 30-9. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 30.6.3.3 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start.
Figure 30-11.
30.6.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 305. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd.
30.6.3.6 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
Table 30-7. 30.6.3.8 Maximum Timeguard Length Depending on Baud Rate (Continued) Baud Rate Bit time Timeguard 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line.
Table 30-8 gives the maximum time-out period for some standard baud rates. Table 30-8. 30.6.3.9 Maximum Time-out Period Baud Rate Bit Time Time-out bit/sec µs ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 Framing Error The receiver is capable of detecting framing errors.
A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed.
Figure 30-17. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2.
30.6.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 295). The USART connects to a smart card as shown in Figure 30-20. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin.
Figure 30-22. T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 30.6.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. 30.6.4.
in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 30-23. Connection to IrDA Transceivers USART IrDA Transceivers Receiver Demodulator RXD Transmitter Modulator TXD RX TX The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: 30.6.5.
Figure 30-24. IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 0 1 1 0 0 1 1 0 1 TXD 3 16 Bit Period Bit Period 30.6.5.2 IrDA Baud Rate Table 30-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 30-10. IrDA Baud Rate Error Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.
30.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
30.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 30-26. Figure 30-26.
30.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI.
30.6.8.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 30-29. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 30-29. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 30.6.8.
30.7 Universal Synchronous Asynchronous Receiver Transeiver (USART) User Interface Table 30-12.
30.7.1 USART Control Register Name: US_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect.
• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
30.7.
0 1 6 bits 1 0 7 bits 1 1 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • PAR: Parity Type PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode • NBSTOP: Number of Stop Bits NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.
• CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
30.7.
30.7.
30.7.
30.7.6 USART Channel Status Register Name: US_CSR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITERATION 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled.
• PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. • DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. • DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. • CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1.
30.7.7 USART Receive Holding Register Name: US_RHR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
30.7.8 USART Transmit Holding Register Name: US_THR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
30.7.
30.7.10 USART Receiver Time-out Register Name: US_RTOR Access Type: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
30.7.11 USART Transmitter Timeguard Register Name: US_TTGR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
30.7.12 USART FI DI RATIO Register Name: US_FIDI Access Type: Read-write Reset Value : 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 30.7.
30.7.14 USART IrDA FILTER Register Name: US_IF Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
31. Synchronous Serial Controller (SSC) 31.1 Overview The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
31.3 Application Block Diagram Figure 31-2. Application Block Diagram OS or RTOS Driver Power Management Interrupt Management Test Management SSC Serial AUDIO 31.4 Codec Time Slot Management Frame Management Line Interface Pin Name List Table 31-1.
The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins.
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 31.6.1.1 Clock Divider Figure 31-4.
Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 31-6. Transmitter Clock Management SSC_TCMR.CKS SSC_TCMR.CKO TK Receiver Clock TK Divider Clock 0 Transmitter Clock 1 SSC_TCMR.CKI 31.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad.
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR.
Figure 31-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF Start Selector SSC_RFMR.MSBF SSC_RFMR.DATNB Receive Shift Register SSC_RSHR SSC_RHR SSC_RFMR.FSLEN SSC_RFMR.DATLEN RD SSC_RCMR.STTDLY 31.6.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR.
Figure 31-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF TD (Output) TD (Output) X BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) TD (Output) B1 STTDLY BO X B1 STTDLY TD Start = Level Change on TF (Output) Start = Any Edge on TF BO BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 31-11.
31.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. Programmable low or high levels during data transfer are supported. Programmable high levels before the start of data transfers or toggling are also supported.
31.6.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: the event that starts the data transfer (START) the delay in number of bit periods between the start event and the first data bit (STTDLY) the length of the data (DATLEN) the number of data to be transferred for each start event (DATNB).
Table 31-3.
Figure 31-15. Receive Frame Format in Continuous Mode Start = Enable Receiver Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN RD Note: 1. STTDLY is set to 0. 31.6.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 31.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers.
31.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 31-17. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB MSB Right Channel Left Channel Figure 31-18.
Figure 31-19.
31.8 Synchronous Serial Controller (SSC) User Interface Table 31-4.
31.8.1 SSC Control Register Name: SSC_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0: No effect. 1: Disables Receive. If a character is currently being received, disables at end of current character reception.
31.8.2 SSC Clock Mode Register Name: SSC_CMR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV • DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
31.8.
• CKG: Receive Clock Gating Selection CKG Receive Clock Gating 0x0 None, continuous clock 0x1 Receive Clock enabled only if RF Low 0x2 Receive Clock enabled only if RF High 0x3 Reserved • START: Receive Start Selection START Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
31.8.4 SSC Receive Frame Mode Register Name: SSC_RFMR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver.
• FSOS: Receive Frame Sync Output Selection FSOS Selected Receive Frame Sync Signal RF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Input-only Reserved Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
31.8.
• CKG: Transmit Clock Gating Selection CKG Transmit Clock Gating 0x0 None, continuous clock 0x1 Transmit Clock enabled only if TF Low 0x2 Transmit Clock enabled only if TF High 0x3 Reserved • START: Transmit Start Selection START Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
31.8.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 23 FSDEN 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit.
• FSOS: Transmit Frame Sync Output Selection FSOS Selected Transmit Frame Sync Signal TF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Input-only Reserved Undefined • FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal.
31.8.7 SSC Receive Holding Register Name: SSC_RHR Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 31.8.
31.8.9 SSC Receive Synchronization Holding Register Name: SSC_RSHR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT • RSDAT: Receive Synchronization Data 31.8.
31.8.
31.8.
31.8.13 SSC Status Register Name: SSC_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty.
• CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register. • TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register.
31.8.14 SSC Interrupt Enable Register Name: SSC_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Empty Interrupt.
• CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt.
31.8.15 SSC Interrupt Disable Register Name: SSC_IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Empty Interrupt.
• CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt.
31.8.16 SSC Interrupt Mask Register Name: SSC_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled.
• CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled. • RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled.
32. Timer Counter (TC) 32.1 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
32.2 Block Diagram Figure 32-1.
32.3 Pin Name List Table 32-3. 32.4 TC pin list Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O Product Dependencies 32.4.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 32.4.
32.5 Functional Description 32.5.1 TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 32-4 on page 389. 32.5.2 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
Figure 32-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK2 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 32-3.
32.5.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 32-4. The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR.
MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST CLKI S R OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS INT Figure 32-5.
32.5.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST TCCLKS Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TIOB MTIOB TIOA MTIOA Figur
32.5.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 32-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 32-8. RC Compare cannot be programmed to generate a trigger in this configuration.
32.5.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 32-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 32-10.
32.5.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 32-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 32-12.
32.5.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 32-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 32-14.
32.5.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
32.6 Timer Counter (TC) User Interface Table 32-4.
32.6.1 TC Block Control Register Register Name: TC_BCR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
32.6.
32.6.3 TC Channel Control Register Register Name: TC_CCR [x=0..2] Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock.
32.6.4 TC Channel Mode Register: Capture Mode Register Name: TC_CMRx [x=0..
• ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. • WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled).
32.6.5 TC Channel Mode Register: Waveform Mode Register Name: TC_CMRx [x=0..
• EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • EEVT: External Event Selection EEVT Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
• ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPC: RC Compare Effect on TIOB BCPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle SAM7X
• BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle SAM7X Series [DATASHEET] 6120K–ATARM–11-Feb-14 398
32.6.6 TC Counter Value Register Register Name: TC_CVx [x=0..2] Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time. 32.6.7 TC Register A Register Name: TC_RAx [x=0..
32.6.8 TC Register B Register Name: TC_RB [x=0..2] Access Type: Read-only if WAVE = 0, Read-write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time.
32.6.9 TC Register C Register Name: TC_RCx [x=0..2] Access Type: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time.
32.6.10 TC Status Register Register Name: TC_SRx [x=0..2] Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register.
• CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high.
32.6.11 TC Interrupt Enable Register Register Name: TC_IERx [x=0..2] Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt.
32.6.12 TC Interrupt Disable Register Register Name: TC_IDR [x=0..2] Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect.
32.6.13 TC Interrupt Mask Register Register Name: TC_IMRx [x=0..2] Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled.
33. Pulse Width Modulation Controller (PWM) 33.1 Overview The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
33.3 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 33-1. 33.4 I/O Line Description Name Description Type PWMx PWM Waveform Output for channel x Output Product Dependencies 33.4.1 I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function.
33.5.1 PWM Clock Generator Figure 33-2. Functional View of the Clock Generator Block Diagram MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A PREA clkA DIVA PWM_MR Divider B PREB clkB DIVB PWM_MR Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC).
33.5.2 PWM Channel 33.5.2.1 Block Diagram Figure 33-3. Functional View of the Channel Block Diagram inputs from clock generator Channel Clock Selector Internal Counter Comparator PWMx output waveform inputs from APB bus Each of the 4 channels is composed of three blocks: 33.5.2.2 A clock selector which selects one of the clocks provided by the clock generator described in Section 33.5.1 “PWM Clock Generator” on page 409. An internal counter clocked by the output of the clock selector.
(--------------------------------------------------2 × CPRD × DIVA ) ( 2 × CPRD × DIVB ) or --------------------------------------------------MCK MCK the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
Figure 33-5. Waveform Properties PWM_MCKx CHIDx(PWM_SR) CHIDx(PWM_ENA) CHIDx(PWM_DIS) Center Aligned CALG(PWM_CMRx) = 1 PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Period Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) Left Aligned CALG(PWM_CMRx) = 0 PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Period Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) 33.5.3 PWM Controller Operations 33.5.3.
Configuration of the clock generator if DIVA and DIVB are required Selection of the clock for each channel (CPRE field in the PWM_CMRx register) Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx Register is possible while the channel is disabled.
To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level. The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the enabled channel(s). See Figure 33-7. The second method uses an Interrupt Service Routine associated with the PWM channel.
33.6 Pulse Width Modulation Controller (PWM) User Interface Table 33-2.
33.6.1 PWM Mode Register Register Name: PWM_MR Access Type: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 PREB 19 18 10 DIVB 15 – 14 – 13 – 12 – 11 7 6 5 4 3 PREA 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB CLKA, CLKB 0 CLKA, CLKB clock is turned off 1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
33.6.2 PWM Enable Register Register Name: PWM_ENA Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x.
33.6.3 PWM Disable Register Register Name: PWM_DIS Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x.
33.6.4 PWM Status Register Register Name: PWM_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
33.6.5 PWM Interrupt Enable Register Register Name: PWM_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x.
33.6.6 PWM Interrupt Disable Register Register Name: PWM_IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x.
33.6.7 PWM Interrupt Mask Register Register Name: PWM_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled.
33.6.8 PWM Interrupt Status Register Register Name: PWM_ISR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
33.6.9 PWM Channel Mode Register Register Name: PWM_CMR[0..
33.6.10 PWM Channel Duty Cycle Register Register Name: PWM_CDTY[0..X-1] Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
33.6.11 PWM Channel Period Register Register Name: PWM_CPRD[0. X-1] Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 16 bits (internal channel counter size) are significant.
33.6.12 PWM Channel Counter Register Register Name: PWM_CCNT[0..X-1] Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register). • the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
33.6.13 PWM Channel Update Register Register Name: PWM_CUPD[0..X-1] Access Type: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle. Only the first 16 bits (internal channel counter size) are significant.
34. USB Device Port (UDP) 34.1 Overview The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the MCK domain and a 48 MHz clock used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode.
34.4 Typical Connection Figure 34-2. Board Schematic to Interface USB Device Peripheral PIO 5V Bus Monitoring 27 K 47 K 3V3 PIO Pullup Control 0: Enable 1: Disable 1.5K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 330 K 330 K 34.4.1 USB Device Transceiver The USB device transceiver is embedded in the product.
34.5 Functional Description 34.5.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 34-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.
34.5.1.2 USB Bus Transactions Each transfer results in one or more transactions over the USB bus. There are three kinds of transactions flowing across the bus in packets: 1. 34.5.1.3 Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 34-3.
Figure 34-4. Control Read and Write Sequences Setup Stage Control Read Setup TX Data Stage Data OUT TX Setup Stage Control Write No Data Control Notes: Setup TX Status Stage Data OUT TX Data Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Status IN TX Status Stage Data IN TX Status OUT TX 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID.
Figure 34-5. Setup Transaction Followed by a Data OUT Transaction Setup Received USB Bus Packets Setup PID Data Setup Setup Handled by Firmware ACK PID RXSETUP Flag Data OUT PID Data OUT Data Out Received NAK PID ACK PID Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) 34.5.2.
Figure 34-6.
1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_ CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_ FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s UDP_ CSRx register. 4.
1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s UDP_ CSRx register.
Figure 34-10.
Figure 34-11.
Figure 34-12. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 34-13.
34.5.2.5 Transmit Data Cancellation Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availablity refer to Table 34-1 ”USB Endpoint Description”. Endpoints Without Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.
34.5.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 34-14.
34.5.3.2 Entering Attached State When no device is connected, the USB DP and DM signals are tied to GND by 15 KΩ pull-down resistors integrated in the hub downstream ports. When a device is attached to a hub downstream port, the device connects a 1.5 KΩ pull-up resistor on DP. The USB bus line goes into IDLE state, DP is pulled up by the device 1.5 KΩ resistor to 3.3V and DM is pulled down by the 15 KΩ resistor of the host. After pullup connection, the device enters the powered state.
Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral.
34.6 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register. Table 34-4.
34.6.1 UDP Frame Number Register Register Name: UDP_ FRM_NUM Access Type: Read-only 31 --- 30 --- 29 --- 28 --- 27 --- 26 --- 25 --- 24 --- 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
34.6.2 UDP Global State Register Register Name: UDP_ GLB_STAT Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 – 3 – 2 – 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state.
34.6.3 UDP Function Address Register Register Name: UDP_ FADDR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.
34.6.
34.6.
34.6.
34.6.
• SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence.
34.6.8 UDP Interrupt Clear Register Register Name: UDP_ ICR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 – 9 RXRSM 8 RXSUSP 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt.
34.6.
34.6.10 UDP Endpoint Control and Status Register Register Name: UDP_ CSRx [x = 0..
• RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0. 1 = A data packet has been received, it has been stored in the FIFO's Bank 0.
1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. • TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = Can be set to one to send the FIFO data. 1 = The data is waiting to be sent upon reception of token IN. Write: 0 = Can be written if old value is zero.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. • DIR: Transfer Direction (only available for control endpoints) Read/Write 0 = Allows Data OUT transactions in the control data stage.
34.6.11 UDP FIFO Data Register Register Name: UDP_ FDRx [x = 0..5] Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_ CSRx register is the number of bytes to be read from the FIFO (sent by the host).
34.6.12 UDP Transceiver Control Register Register Name: UDP_ TXVC Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register.
35. Analog-to-Digital Converter (ADC) 35.1 Overview The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital conversions of 8 analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
35.3 Signal Description Table 35-1. ADC Pin Description Pin Name Description ADVREF Reference voltage AD0 - AD7 Analog input channels ADTRG External trigger 35.4 Product Dependencies 35.4.1 Power Management The ADC Controller clock (MCK) is always clocked. 35.4.2 Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the ADC interrupt requires the AIC to be programmed first. 35.4.
35.5 Functional Description 35.5.1 Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the “ADC Mode Register” on page 472 and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F).
35.5.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt.
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (ADC_SR). In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in ADC_SR. The OVRE and GOVRE flags are automatically cleared when ADC_SR is read. Figure 35-3.
35.5.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR).
35.5.7 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register ADC_MR. In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC.
35.6 Analog-to-Digital Converter (ADC) User Interface Table 35-2.
35.6.1 ADC Control Register Register Name: ADC_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 START 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion.
35.6.2 ADC Mode Register Register Name: ADC_MR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 23 – 22 21 20 19 STARTUP 15 14 13 12 26 25 24 18 17 16 11 10 9 8 3 2 TRGSEL 1 0 TRGEN SHTIM PRESCAL 7 – 6 – 5 SLEEP 4 LOWRES • TRGEN: Trigger Enable TRGEN Selected TRGEN 0 Hardware triggers are disabled. Starting a conversion is only possible by software. 1 Hardware trigger selected by TRGSEL field is enabled.
• PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 ) • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock • SHTIM: Sample & Hold Time Sample & Hold Time = SHTIM/ADCClock SAM7X Series [DATASHEET] 6120K–ATARM–11-Feb-14 473
35.6.3 ADC Channel Enable Register Register Name: ADC_CHER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel. 35.6.
35.6.5 ADC Channel Status Register Register Name: ADC_CHSR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
35.6.6 ADC Status Register Register Name: ADC_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RXBUFF 18 ENDRX 17 GOVRE 16 DRDY 15 OVRE7 14 OVRE6 13 OVRE5 12 OVRE4 11 OVRE3 10 OVRE2 9 OVRE1 8 OVRE0 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished. 1 = Corresponding analog channel is enabled and conversion is complete.
35.6.7 ADC Last Converted Data Register Register Name: ADC_LCDR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 LDATA 0 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. 35.6.
35.6.
35.6.
35.6.11 ADC Channel Data Register Register Name: ADC_CDRx Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 DATA 0 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
36. Controller Area Network (CAN) 36.1 Overview The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/sec. CAN controller accesses are made through configuration registers.
36.2 Block Diagram Figure 36-1.
36.3 Application Block Diagram Figure 36-2. 36.4 Application Block Diagram Layers Implementation CAN-based Profiles Software CAN-based Application Layer Software CAN Data Link Layer CAN Controller CAN Physical Layer Transceiver I/O Lines Description Table 36-1. I/O Lines Description Name Description Type CANRX CAN Receive Serial Data Input CANTX CAN Transmit Serial Data Output 36.5 Product Dependencies 36.5.
36.6 CAN Controller Features 36.6.1 CAN Protocol Overview The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports real-time control with a very high level of security with bit rates up to 1 Mbit/s. The CAN protocol supports four different frame types: Data frames: They carry data from a transmitter node to the receiver nodes. The overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame.
Figure 36-3. Message Acceptance Procedure CAN_MAMx CAN_MIDx & Message Received & == No Message Refused Yes Message Accepted CAN_MFIDx If a mailbox is dedicated to receiving several messages (a family of messages) with different IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the CAN_MIDx.
It is also possible to configure a mailbox in Consumer Mode. In this mode, after each transfer request, a remote frame is automatically sent. The first answer received is stored in the corresponding mailbox data registers. Several mailboxes can be chained to receive a buffer. They must be configured with the same ID in Receive Mode, except for the last one, which can be configured in Receive with Overwrite Mode. The last mailbox can be used to detect a buffer overflow.
36.6.3 Time Management Unit The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR register).
36.6.4 CAN 2.0 Standard Features 36.6.4.1 CAN Bit Timing Configuration All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments. The CAN protocol specification partitions the nominal bit time into four different segments: Figure 36-4.
In the CAN controller, the length of a bit on the CAN bus is determined by the parameters (BRP, PROPAG, PHASE1 and PHASE2). t BIT = t CSC + t PRS + t PHS1 + t PHS2 The time quantum is calculated as follows: t CSC = ( BRP + 1 ) ⁄ MCK Note: The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized.
Tphs1 + Tphs2 = 12 Tcsc Because this number is even, we choose Tphs2 = Tphs1 (else we would choose Tphs2 = Tphs1 + Tcsc) Tphs1 = Tphs2 = (12/2) Tcsc = 6 Tcsc => PHASE1 = PHASE2 = Tphs1/Tcsc - 1 = 5 The resynchronization jump width must be comprised between 1 Tcsc and the minimum of 4 Tcsc and Tphs1. We choose its maximum value: Tsjw = Min(4 Tcsc,Tphs1) = 4 Tcsc => SJW = Tsjw/Tcsc - 1 = 3 Finally: CAN_BR = 0x00053255 36.6.4.
Figure 36-6.
36.6.4.5 Fault Confinement To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The two counters are incremented upon detected errors and are decremented upon correct transmissions or receptions, respectively. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active flags.
ERRP = 0 BOFF = 0 In Error Passive Mode, the user reads: ERRA = 0 ERRP =1 BOFF = 0 In Bus Off Mode, the user reads: ERRA = 0 ERRP =1 BOFF =1 The CAN interrupt handler should do the following: 36.6.4.7 Only enable one error mode interrupt at a time. Look at and check the REC and TEC values in the interrupt handler to determine the current state.
Thus, to enter Low-power Mode, the software application must: Set LPM field in the CAN_MR register Wait for SLEEP signal rising Now the CAN Controller clock can be disabled. This is done by programming the Power Management Controller (PMC). Figure 36-8. Enabling Low-power Mode Arbitration lost Mailbox 1 CAN BUS Mailbox 3 LPEN= 1 LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSR1) MRDY (CAN_MSR3) CAN_TIM 36.6.5.
Figure 36-9. Disabling Low-power Mode Bus Activity Detected CAN BUS Message lost LPM (CAN_MR) Message x Interframe synchronization SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSRx) 36.7 Functional Description 36.7.1 CAN Controller Initialization After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller (AIC).
Figure 36-10. Possible Initialization Procedure Enable CAN Controller Clock (PMC) Enable CAN Controller Interrupt Line (AIC) Configure a Mailbox in Reception Mode Change CAN_BR value (ABM == 1 and CANEN == 1) Errors ? Yes (CAN_SR or CAN_MSRx) No ABM = 0 and CANEN = 0 CANEN = 1 (ABM == 0) End of Initialization 36.7.2 CAN Controller Interrupt Handling There are two different types of interrupts.
Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register. All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the CAN_SR register. 36.7.3 CAN Controller Message Handling 36.7.3.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt is masked depending on the mailbox flag in the CAN_IMR global register. If a new message is received while the MRDY flag is set, this new message is stored in the mailbox data register, overwriting the previous message.
Figure 36-13.
36.7.3.5 Transmission Handling A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled. After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers.
Figure 36-15. Transmitting Messages MBx message CAN BUS MBx message MRDY (CAN_MSRx) MABT (CAN_MSRx) MTCR (CAN_MCRx) MACR (CAN_MCRx) Abort MBx message Try to Abort MBx message Reading CAN_MSRx Writing CAN_MDHx & CAN_MDLx 36.7.3.6 Remote Frame Handling Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages. Figure 36-16.
36.7.3.7 Producer Configuration A mailbox is in Producer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Producer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx register.
the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR register. Figure 36-18. Consumer Handling CAN BUS Remote Frame Message x Remote Frame Message y MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) (CAN_MDLx CAN_MDHx) Message y Message x 36.7.
36.7.4.2 Time Triggered Mode In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a predefined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window. Figure 36-20.
Figure 36-21.
36.8 Controller Area Network (CAN) User Interface Table 36-2.
36.8.1 CAN Mode Register Name: CAN_MR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 25 RXSYNC 24 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 DRPT 6 TIMFRZ 5 TTM 4 TEOF 3 OVL 2 ABM 1 LPM 0 CANEN • CANEN: CAN Controller Enable 0 = The CAN Controller is disabled. 1 = The CAN Controller is enabled. • LPM: Disable/Enable Low Power Mode w Power Mode.
0 = When a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1 = When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx.
36.8.2 CAN Interrupt Enable Register Name: CAN_IER Access Type: Write-only 31 – 30 – 29 – 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Interrupt Enable 0 = No effect. 1 = Enable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Enable 0 = No effect. 1 = Enable ERRA interrupt.
• TSTP: TimeStamp Interrupt Enable 0 = No effect. 1 = Enable TSTP interrupt. • CERR: CRC Error Interrupt Enable 0 = No effect. 1 = Enable CRC Error interrupt. • SERR: Stuffing Error Interrupt Enable 0 = No effect. 1 = Enable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Enable 0 = No effect. 1 = Enable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Enable 0 = No effect. 1 = Enable Form Error interrupt. • BERR: Bit Error Interrupt Enable 0 = No effect.
36.8.3 CAN Interrupt Disable Register Name: CAN_IDR Access Type: Write-only 31 – 30 – 29 – 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Interrupt Disable 0 = No effect. 1 = Disable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Disable 0 = No effect. 1 = Disable ERRA interrupt.
• TSTP: TimeStamp Interrupt Disable 0 = No effect. 1 = Disable TSTP interrupt. • CERR: CRC Error Interrupt Disable 0 = No effect. 1 = Disable CRC Error interrupt. • SERR: Stuffing Error Interrupt Disable 0 = No effect. 1 = Disable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Disable 0 = No effect. 1 = Disable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Disable 0 = No effect. 1 = Disable Form Error interrupt. • BERR: Bit Error Interrupt Disable 0 = No effect.
36.8.4 CAN Interrupt Mask Register Name: CAN_IMR Access Type: Read-only 31 – 30 – 29 – 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Interrupt Mask 0 = Mailbox x interrupt is disabled. 1 = Mailbox x interrupt is enabled. • ERRA: Error Active Mode Interrupt Mask 0 = ERRA interrupt is disabled.
• TSTP: Timestamp Interrupt Mask 0 = TSTP interrupt is disabled. 1 = TSTP interrupt is enabled. • CERR: CRC Error Interrupt Mask 0 = CRC Error interrupt is disabled. 1 = CRC Error interrupt is enabled. • SERR: Stuffing Error Interrupt Mask 0 = Bit Stuffing Error interrupt is disabled. 1 = Bit Stuffing Error interrupt is enabled. • AERR: Acknowledgment Error Interrupt Mask 0 = Acknowledgment Error interrupt is disabled. 1 = Acknowledgment Error interrupt is enabled.
36.8.5 CAN Status Register Name: CAN_SR Access Type: Read-only 31 OVLSY 30 TBSY 29 RBSY 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Event 0 = No event occurred on Mailbox x. 1 = An event occurred on Mailbox x. An event corresponds to MRDY, MABT fields in the CAN_MSRx register.
This flag is set depending on TEC counter value. A node is bus off when TEC counter is greater or equal to 256 (decimal). This flag is automatically reset when above condition is not satisfied. Refer to Section 36.6.4.6 “Error Interrupt Handler” on page 492 for more information. • SLEEP: CAN controller in Low power Mode 0 = CAN controller is not in low power mode. 1 = CAN controller is in low power mode.
A form error results from violations on one or more of the fixed form of the following bit fields: – CRC delimiter – ACK delimiter – End of frame – Error delimiter – Overload delimiter This flag is automatically cleared by reading CAN_SR register. • BERR: Bit Error 0 = No bit error occurred during a previous transfer. 1 = A bit error occurred during a previous transfer. A bit error is set when the bit value monitored on the line is different from the bit value sent.
36.8.6 CAN Baudrate Register Name: CAN_BR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 SMP 23 – 22 21 20 19 BRP 18 17 16 15 – 14 – 13 12 11 – 10 9 PROPAG 8 7 – 6 5 PHASE1 4 3 – 2 1 PHASE2 0 SJW Any modification on one of the fields of the CANBR register must be done while CAN module is disabled. To compute the different Bit Timings, please refer to the Section 36.6.4.1 “CAN Bit Timing Configuration” on page 488.
36.8.7 CAN Timer Register Name: CAN_TIM Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TIMER15 14 TIMER14 13 TIMER13 12 TIMER12 11 TIMER11 10 TIMER10 9 TIMER9 8 TIMER8 7 TIMER7 6 TIMER6 5 TIMER5 4 TIMER4 3 TIMER3 2 TIMER2 1 TIMER1 0 TIMER0 • TIMERx: Timer This field represents the internal CAN controller 16-bit timer value.
36.8.
36.8.9 CAN Error Counter Register Name: CAN_ECR Access Type: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 TEC 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 REC • REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG.
36.8.10 CAN Transfer Command Register Name: CAN_TCR Access Type: Write-only 31 TIMRST 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 This register initializes several transfer requests at the same time. • MBx: Transfer Request for Mailbox x Mailbox Object Type Description Receive It receives the next message.
36.8.11 CAN Abort Command Register Name: CAN_ACR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 This register initializes several abort requests at the same time.
36.8.12 CAN Message Mode Register Name: CAN_MMRx Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 23 – 22 – 21 – 20 – 19 18 25 24 MOT 17 16 PRIOR 15 14 13 12 11 10 9 8 MTIMEMARK15 MTIMEMARK14 MTIMEMARK13 MTIMEMARK12 MTIMEMARK11 MTIMEMARK10 MTIMEMARK9 MTIMEMARK8 7 6 5 4 3 2 1 0 MTIMEMARK7 MTIMEMARK6 MTIMEMARK5 MTIMEMARK4 MTIMEMARK3 MTIMEMARK2 MTIMEMARK1 MTIMEMARK0 • MTIMEMARK: Mailbox Timemark This field is active in Time Triggered Mode.
36.8.13 CAN Message Acceptance Mask Register Name: CAN_MAMx Access Type: Read-write 31 – 30 – 29 MIDE 23 22 21 28 27 26 MIDvA 25 20 19 18 17 MIDvA 15 14 13 24 16 MIDvB 12 11 10 9 8 3 2 1 0 MIDvB 7 6 5 4 MIDvB To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MAMx registers.
36.8.14 CAN Message ID Register Name: CAN_MIDx Access Type: Read-write 31 – 30 – 29 MIDE 23 22 21 28 27 26 MIDvA 25 20 19 18 17 MIDvA 15 14 13 24 16 MIDvB 12 11 10 9 8 3 2 1 0 MIDvB 7 6 5 4 MIDvB To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MIDx registers. • MIDvB: Complementary bits for identifier in extended frame mode If MIDE is cleared, MIDvB value is 0.
36.8.15 CAN Message Family ID Register Name: CAN_MFIDx Access Type: Read-only 31 – 30 – 29 – 28 23 22 21 20 27 26 MFID 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MFID 15 14 13 12 MFID 7 6 5 4 MFID • MFID: Family ID This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx register. This field is useful to speed up message ID decoding. The message acceptance procedure is described below.
36.8.
• MRTR: Mailbox Remote Transmission Request Mailbox Object Type Description Receive The first frame received has the RTR bit set. Receive with overwrite The last frame received has the RTR bit set. Transmit Reserved Consumer Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 1. Producer Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 0. • MABT: Mailbox Message Abort An interrupt is triggered when MABT is set. 0 = Previous transfer is not aborted.
• MMI: Mailbox Message Ignored 0 = No message has been ignored during the previous transfer 1 = At least one message has been ignored during the previous transfer Cleared by reading the CAN_MSRx register. Mailbox Object Type Description Receive Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message.
36.8.17 CAN Message Data Low Register Name: CAN_MDLx Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MDL 23 22 21 20 MDL 15 14 13 12 MDL 7 6 5 4 MDL • MDL: Message Data Low Value When MRDY field is set in the CAN_MSRx register, the lower 32 bits of a received message can be read or written by the software application. Otherwise, the MDL value is locked by the CAN controller to send/receive a new message.
36.8.18 CAN Message Data High Register Name: CAN_MDHx Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MDH 23 22 21 20 MDH 15 14 13 12 MDH 7 6 5 4 MDH • MDH: Message Data High Value When MRDY field is set in the CAN_MSRx register, the upper 32 bits of a received message are read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message.
36.8.19 CAN Message Control Register Name: CAN_MCRx Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 23 MTCR 22 MACR 21 – 20 MRTR 19 18 15 – 14 13 – 12 11 – 7 – 6 5 – 4 3 – – – – – 25 24 – – 17 16 10 9 – – 8 – 2 – 1 0 – – MDLC • MDLC: Mailbox Data Length Code Mailbox Object Type Description Receive No action. Receive with overwrite No action. Transmit Length of the mailbox message. Consumer No action.
• MACR: Abort Request for Mailbox x Mailbox Object Type Description Receive No action Receive with overwrite No action Transmit Cancels transfer request if the message has not been transmitted to the CAN transceiver. Consumer Cancels the current transfer before the remote frame has been sent. Producer Cancels the current transfer. The next remote frame will not be serviced. It is possible to set MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR register.
37. Ethernet MAC 10/100 (EMAC) 37.1 Overview The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal.
37.3 Functional Description The EMAC has several clock domains: System bus clock (AHB and APB): DMA and register blocks Transmit clock: transmit block Receive clock: receive and address checker blocks The only system constraint is 160 MHz for the system bus clock, above which MDC would toggle at above 2.5 MHz. The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps).
At 100 Mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. In addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 60 MHz master clock this takes 100 ns, making the bus latency requirement 860 ns. 37.3.1.2 Receive Buffers Received frames, including CRC/FCS optionally, are written to receive buffers stored in memory. Each receive buffer is 128 bytes long.
Table 37-1. Bit Receive Buffer Descriptor Entry (Continued) Function 14 Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame. 13:12 Receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. Updated with the current values of the network configuration register.
37.3.1.3 Transmit Buffer Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in IEEE Standard 802.3. Zero length buffers are allowed. The maximum number of buffers permitted for each transmit frame is 128.
Table 37-2. Transmit Buffer Descriptor Entry (Continued) Bit Function Used. Needs to be zero for the EMAC to read data from the transmit buffer. The EMAC sets this to one for the first buffer of a frame once it has been successfully transmitted. Software has to clear this bit before the buffer can be used again. 31 Note: This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used. 30 Wrap.
37.3.3 Pause Frame Support The start of an 802.3 pause frame is as follows: Table 37-3. Start of an 802.3 Pause Frame Destination Address Source Address Type (Mac Control Frame) Pause Opcode Pause Time 0x0180C2000001 6 bytes 0x8808 0x0001 2 bytes The network configuration register contains a receive pause enable bit (13).
group/individual bit: this is One for multicast addresses and Zero for unicast. The All Ones address is the broadcast address, and a special case of multicast. The EMAC supports recognition of four specific addresses. Each specific address requires two registers, specific address register bottom and specific address register top. Specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes.
hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] d
37.3.11 PHY Maintenance The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are configured for the same speed and duplex configuration. The PHY maintenance register is implemented as a shift register.
37.4 Programming Interface 37.4.1 Initialization 37.4.1.1 Configuration Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document. To change loop-back mode, the following sequence of operations must be followed: 1. Write to network control register to disable transmit and receive circuits. 2.
37.4.1.4 1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. 2. Allocate an area 2n words for the transmit buffer descriptor entry in system memory and create N entries in this list. Mark all entries in this list as owned by EMAC, i.e. bit 31 of word 1 set to 0. 3. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit — bit 30 in word 1 set to 1. 4.
set. Software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. If there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not available is set.
37.5 Ethernet MAC 10/100 (EMAC) User Interface Table 37-6.
Table 37-6.
37.5.1 Network Control Register Register Name: EMAC_NCR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TE 2 RE 1 LLB 0 LB • LB: LoopBack Asserts the loopback signal to the PHY. • LLB: Loopback Local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4.
37.5.2 Network Configuration Register Register Name: EMAC_NCFGR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 IRXFCS 18 EFRHD 17 DRFCS 16 RLCE 14 13 PAE 12 RTY 11 10 9 8 BIG 5 NBC 4 CAF 3 JFRAME 2 – 1 FD 0 SPD 15 RBOF 7 UNI 6 MTI CLK • SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s.
• CLK: MDC clock divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations). CLK MDC 00 MCK divided by 8 (MCK up to 20 MHz) 01 MCK divided by 16 (MCK up to 40 MHz) 10 MCK divided by 32 (MCK up to 80 MHz) 11 MCK divided by 64 (MCK up to 160 MHz) • RTY: Retry test Must be set to zero for normal operation.
37.5.3 Network Status Register Register Name: EMAC_NSR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – • MDIO Returns status of the MDIO pin. Use the PHY maintenance register for reading managed frames rather than this bit. • IDLE 0 = The PHY logic is running. 1 = The PHY management logic is idle (i.e., has completed).
37.5.4 Transmit Status Register Register Name: EMAC_TSR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UND 5 COMP 4 BEX 3 TGO 2 RLE 1 COL 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
37.5.5 Receive Buffer Queue Pointer Register Register Name: EMAC_RBQP Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
37.5.6 Transmit Buffer Queue Pointer Register Register Name: EMAC_TBQP Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
37.5.7 Receive Status Register Register Name: EMAC_RSR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 OVR 1 REC 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
37.5.8 Interrupt Status Register Register Name: EMAC_ISR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. • RCOMP: Receive Complete A frame has been stored in memory. Cleared on read.
37.5.9 Interrupt Enable Register Register Name: EMAC_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Enable management done interrupt. • RCOMP: Receive Complete Enable receive complete interrupt. • RXUBR: Receive Used Bit Read Enable receive used bit read interrupt.
37.5.10 Interrupt Disable Register Register Name: EMAC_IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Disable management done interrupt. • RCOMP: Receive Complete Disable receive complete interrupt. • RXUBR: Receive Used Bit Read Disable receive used bit read interrupt.
37.5.11 Interrupt Mask Register Register Name: EMAC_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Management done interrupt masked. • RCOMP: Receive Complete Receive complete interrupt masked. • RXUBR: Receive Used Bit Read Receive used bit read interrupt masked.
37.5.12 PHY Maintenance Register Register Name: EMAC_MAN Access Type: Read-write 31 30 29 SOF 28 27 26 RW 23 PHYA 22 15 14 21 13 25 24 PHYA 20 REGA 19 18 17 16 CODE 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA • DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. • CODE: Must be written to 10. Reads as written. • REGA: Register Address Specifies the register in the PHY to access.
37.5.13 Pause Time Register Register Name: EMAC_PTR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PTIME 7 6 5 4 PTIME • PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
37.5.14 Hash Register Bottom Register Name: EMAC_HRB Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Bits 31:0 of the hash address register. See “Hash Addressing” on page 542. 37.5.
37.5.16 Specific Address 1 Bottom Register Register Name: EMAC_SA1B Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 37.5.
37.5.18 Specific Address 2 Bottom Register Register Name: EMAC_SA2B Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 37.5.
37.5.20 Specific Address 3 Bottom Register Register Name: EMAC_SA3B Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 37.5.
37.5.22 Specific Address 4 Bottom Register Register Name: EMAC_SA4B Access Type: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 37.5.
37.5.24 Type ID Checking Register Register Name: EMAC_TID Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID • TID: Type ID Checking For use in comparisons with received frames TypeID/Length field.
37.5.25 User Input/Output Register Register Name: EMAC_USRIO Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CLKEN 0 RMII • RMII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. • CLKEN When set, this bit enables the transceiver input clock.
37.5.26 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers. 37.5.26.
37.5.26.3 Single Collision Frames Register Register Name: EMAC_SCF Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SCF 7 6 5 4 SCF • SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 37.5.26.
37.5.26.5 Frames Received OK Register Register Name: EMAC_FRO Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 FROK 15 14 13 12 FROK 7 6 5 4 FROK • FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory.
37.5.26.
37.5.26.9 Late Collisions Register Register Name: EMAC_LCOL Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 LCOL • LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision. 37.5.26.
37.5.26.11Transmit Underrun Errors Register Register Name: EMAC_TUND Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TUND • TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented. 37.5.26.
37.5.26.13Receive Resource Errors Register Register Name: EMAC_RRE Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RRE 7 6 5 4 RRE • RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 37.5.26.
37.5.26.15Receive Symbol Errors Register Register Name: EMAC_RSE Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RSE • RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception.
37.5.26.17Receive Jabbers Register Register Name: EMAC_RJA Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RJB • RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. 37.5.26.
37.5.26.19SQE Test Errors Register Register Name: EMAC_STE Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SQER • SQER: SQE Test Errors An 8-bit register counting the number of frames where ECOL was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 37.5.26.
38. SAM7X512/256/128 Electrical Characteristics 38.1 Absolute Maximum Ratings Table 38-1. Absolute Maximum Ratings* Operating Temperature (Industrial).........-40°C to + 85°C Storage Temperature............................-60°C to + 150°C Voltage on Input Pins with Respect to Ground...........................-0.3V to + 5.5V Maximum Operating Voltage (VDDCORE, and VDDPLL)........................................2.
38.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified. Table 38-2. DC Characteristics Symbol Parameter VVDDCORE DC Supply Core VVDDPLL Max Units 1.65 1.95 V DC Supply PLL 1.65 1.95 V VVDDIO DC Supply I/Os 3.0 3.6 V VVDDFLASH DC Supply Flash 3.0 3.6 V VIL Input Low-level Voltage VVDDIO from 3.0V to 3.6V -0.3 0.8 V VIH Input High-level Voltage VVDDIO from 3.0V to 3.6V 2.0 5.
Table 38-3. IVDDIN 1.8V Voltage Regulator Characteristics Current consumption After startup, no load 90 After startup, Idle mode, no load 10 µA 25 µA TSTART Startup Time Cload = 2.2 µF, after VDDIN > 2.7V 150 µS IO Maximum DC Output Current VDDIN = 3.3V 100 mA IO Maximum DC Output Current VDDIN = 3.3V, in Idle Mode 1 mA Table 38-4.
38.3 Power Consumption Typical power consumption of PLLs, Slow Clock and Main Oscillator. Power consumption of power supply in two different modes: Active and ultra Low-power. Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 38.3.
These figures represent the power consumption typically measured on the power supplies.. Table 38-6. Power Consumption for Different Modes Mode Conditions Consumption Unit Voltage regulator is on. Brown Out Detector is activated. Flash is read. ARM Core clock is 50MHz. Active (SAM7X512/256/128) Analog-to-Digital Converter activated. All peripheral clocks activated. USB transceiver enabled. onto AMP1 44 onto AMP2 43 mA Voltage regulator is in Low-power mode. Brown Out Detector is de-activated.
38.4 Crystal Oscillators Characteristics 38.4.1 RC Oscillator Characteristics Table 38-8. RC Oscillator Characteristics Symbol Parameter Conditions 1/(tCPRC) RC Oscillator Frequency VDDPLL = 1.65V Duty Cycle Min Typ Max Unit 22 32 42 kHz 45 50 55 % tST Startup Time VDDPLL = 1.65V 75 µs IOSC Current Consumption After Startup Time 1.
38.4.2 Main Oscillator Characteristics Table 38-9. Main Oscillator Characteristics Symbol Parameter Conditions 1/(tCPMAIN) Crystal Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) CL (6) Equivalent Load Capacitance Integrated Load Capacitance ((XIN or XOUT)) Integrated Load Capacitance (XIN and XOUT in series) Duty Cycle Min Typ Max Unit 3 16 20 MHz 34 40 46 pF 17 20 23 pF 30 50 70 % VDDPLL = 1.
38.4.3 Crystal Characteristics Table 38-10. Symbol ESR Crystal Characteristics Parameter Conditions Equivalent Series Resistor Rs Min Typ Max Fundamental @3 MHz 200 Fundamental @8 MHz 100 Fundamental @16 MHz 80 Fundamental @20 MHz 50 Unit Ω CM Motional capacitance 8 fF CSHUNT Shunt capacitance 7 pF 38.4.4 XIN Clock Characteristics Table 38-11. Symbol XIN Clock Electrical Characteristics Parameter Conditions Min Max Units 50.
38.5 PLL Characteristics Table 38-12. Phase Lock Loop Characteristics Symbol Parameter Conditions FOUT Output Frequency Field out of CKGR_PLL is: FIN Input Frequency IPLL Current Consumption Note: Min Typ Max Unit 00 80 160 MHz 10 150 200 MHz 1 32 MHz Active mode 4 mA Standby mode 1 µA Startup time depends on PLL RC filter. A calculation tool is provided by Atmel.
38.6 USB Transceiver Characteristics 38.6.1 Electrical Characteristics Table 38-13. Symbol Electrical Parameters Parameter Conditions Min Typ Max Unit 0.8 V Input Levels VIL Low Level VIH High Level VDI Differential Input Sensitivity VCM Differential Input Common Mode Range CIN Transceiver capacitance Capacitance to ground on each line I Hi-Z State Data Line Leakage 0V < VIN < 3.
Figure 38-3.
38.7 ADC Characteristics Table 38-15. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency ADC Clock Frequency Startup Time Min Max Units 10-bit resolution mode 5 MHz 8-bit resolution mode 8 MHz Return from Idle Mode 20 µs Track and Hold Acquisition Time Typ 600 ns Conversion Time ADC Clock = 5 MHz 2 µs Conversion Time ADC Clock = 8 MHz 1.
38.8 AC Characteristics 38.8.1 Master Clock Characteristics Table 38-19. Master Clock Waveform Parameters Symbol Parameter Conditions 1/(tCPMCK) Master Clock Frequency Min Max Units 55 MHz 38.8.2 I/O Characteristics Criteria used to define the maximum frequency of the I/Os: output duty cycle (30%-70%) minimum output swing: 100mV to VDDIO - 100mV Addition of rising and falling time inferior to 75% of the period Table 38-20.
38.8.3 SPI Characteristics Figure 38-4. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI0 SPI1 MISO SPI2 MOSI Figure 38-5. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI3 SPI4 MISO SPI5 MOSI Figure 38-6.
Figure 38-7. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI9 MISO SPI10 SPI11 MOSI Table 38-21. Symbol SPI0 SPI1 SPI2 SPI3 SPI4 SPI Timings Parameter MISO Setup time before SPCK rises (master) MISO Hold time after SPCK rises (master) SPCK rising to MOSI Delay (master) MISO Setup time before SPCK falls (master) MISO Hold time after SPCK falls (master) Conditions (1) 3.3V domain Min Max (2) 28.5 + (tCPMCK)/2 (1) 3.3V domain ns 3.3V domain 3.3V domain 3.
38.8.4 EMAC Characteristics Table 38-22. Symbol EMAC1 EMAC Signals Parameter Setup for EMDIO from EMDC rising Conditions Min (ns) (2) 2 (2) ((1/f)-19) + 4(1) Load: 20pF EMAC2 Hold for EMDIO from EMDC rising Load: 20pF EMAC3 EMDIO toggling from EMDC falling Load: 20pF(2) Max (ns) 4.5 Notes: 1. f: MCK frequency (MHz) 2. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF Table 38-23.
Figure 38-8.
Table 38-24. EMAC RMII Specific Signals (Only for SAM7X512) Symbol Parameter Min (ns) Max (ns) EMAC21 ETXEN toggling from EREFCK rising 4.9 14.2 EMAC22 ETX toggling from EREFCK rising 4.4 15.9 EMAC23 Setup for ERX from EREFCK 0.5 EMAC24 Hold for ERX from EREFCK 0 EMAC25 Setup for ERXER from EREFCK 1.5 EMAC26 Hold for ERXER from EREFCK 0 EMAC27 Setup for ECRSDV from EREFCK 2 EMAC28 Hold for ECRSDV from EREFCK 0 Figure 38-9.
38.8.5 Embedded Flash Characteristics The maximum operating frequency is given in Table 38-25 but is limited by the Embedded Flash access time when the processor is fetching code out of it. Table 38-25 gives the device maximum operating frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory. Table 38-25.
38.8.6 JTAG/ICE Timings 38.8.6.1 ICE Interface Signals Table 38-27. Symbol ICE Interface Timing Specification Parameter Conditions Min Max Units 51 ns ICE0 TCK Low Half-period (1) ICE1 TCK High Half-period (1) 51 ns TCK Period (1) 102 ns TDI, TMS, Setup before TCK High (1) 0 ns ICE4 TDI, TMS, Hold after TCK High (1) 3 ns ICE5 TDO Hold Time (1) 13 ns TCK Low to TDO Valid (1) ICE2 ICE3 ICE6 Note: 20 ns 1. VVDDIO from 3.0V to 3.
38.8.6.2 JTAG Interface Signals Table 38-28. Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Note: JTAG Interface Timing specification Parameter Conditions Min TCK Low Half-period (1) Max 6.5 ns TCK High Half-period (1) 5.
39. SAM7X512/256/128 Mechanical Characteristics 39.1 Package Drawings Figure 39-1.
Table 39-1. 100-lead LQFP Package Dimensions Millimeter Symbol Min Nom A Inch Max Min Nom 1.60 A1 0.05 A2 1.35 1.40 0.063 0.15 0.002 1.45 0.053 0.006 0.055 D 16.00 BSC 0.630 BSC D1 14.00 BSC 0.551 BSC E 16.00 BSC 0.630 BSC E1 14.00 BSC R2 0.08 R1 0.08 Q 0° 0° 13° 0° 12° 12° 11° L 0.45 L1 0.20 b 0.17 e 3.5° 7° 11° 12° 13° 12° 0° 0.60 13° 11° 0.20 0.004 0.75 0.018 1.00 REF S 0.008 0.003 7° 11° 0.09 0.003 3.5° θ2 θ3 0.057 0.551 BSC 0.
Figure 39-2. 100-TFBGA Package Drawing All dimensions are in mm Table 39-2. Device and LQFP Package Maximum Weight SAM7X512/256/128 Table 39-3. 800 mg Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification e3 Table 39-4. LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
39.2 Soldering Profile Table 39-5 gives the recommended soldering profile from J-STD-020C. Table 39-5. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260°C Ramp-down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 min. max.
40. AT91SAM7X Ordering Information Table 40-1. Ordering Information MRL A Ordering Code MRL B Ordering Code AT91SAM7X512-AU AT91SAM7X512B-AU – AT91SAM7X512B-AUR AT91SAM7X512-CU AT91SAM7X512B-CU AT91SAM7X256-AU AT91SAM7X256B-AU AT91SAM7X256C-AU LQFP 100 AT91SAM7X256-CU AT91SAM7X256B-CU AT91SAM7X256C-CU TFBGA 100 AT91SAM7X128-AU AT91SAM7X128B-AU AT91SAM7X128C-AU LQFP 100 AT91SAM7X128-CU AT91SAM7X128B-CU AT91SAM7X128C-CU TFBGA 100 Note: 1.
41. SAM7X512/256/128 Errata 41.1 Marking All devices are marked with the Atmel logo and the ordering code.
Errata Summary by Product and Revision or Manufacturing Number Table 41-1. Errata Summary Table Part Errata SAM7X512 rev B SAM7X256/128 rev A SAM7X256/128 rev B SAM7X256/128 rev C SAM7Xx Product Revision or Manufacturing Number SAM7X512 rev A 41.2 Boundary Scan BSDL File for Rev. B Devices Not Compatible with Rev.
Table 41-1.
41.3 AT91SAM7X256/128 Errata - Rev. A Parts Refer to Section 41.1 “Marking” on page 607. Note: AT91SAM7X256 Revision A chip ID is 0x275B 0940. AT91SAM7X128 Revision A chip ID is 0x275A 0740. 41.3.1 Analog-to-Digital Converter (ADC) 41.3.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 41.3.1.
EOC[x] already active, DRDY already active, GOVRE inactive, previous data stored in LCDR being neither data from channel "y", nor data from channel "x". GOVRE should be set but is not. Problem Fix/Workaround None 41.3.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel "y" at the same instant as an end of conversion on channel "x", EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 41.3.1.
41.3.2 Controller Area Network (CAN) 41.3.2.1 CAN: Low Power Mode and Error Frame If the Low Power Mode is activated while the CAN is generating an error frame, this error frame may be shortened. Problem Fix/Workaround None 41.3.2.2 CAN: Low Power Mode and Pending Transmit Messages No pending transmit messages may be sent once the CAN Controller enters Low-power Mode. Problem Fix/Workaround Check that all messages have been sent by reading the related Flags before entering Low-power Mode. 41.3.
41.3.4.2 PIO: Electrical Characteristics on NRST, PA0-PA30 and PB0-PB26 When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.45 V This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.
Do not disable a channel before completion of one period of the selected clock. 41.3.6 Real Time Timer (RTT) 41.3.6.1 RTT: Possible Event Loss when Reading RTT_SR If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event. Problem Fix/Workaround: The software must handle the RTT event as an interrupt and should not poll RTT_SR. 41.3.7 Serial Peripheral Interface (SPI) 41.3.7.
None. 41.3.7.6 SPI: Bad Serial Clock Generation on 2nd Chip Select Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0. This occurs using SPI with the following conditions: Master Mode CPOL = 1 and NCPHA = 0 Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e.
41.3.9 Two-wire Interface (TWI) 41.3.9.1 TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 41.3.9.2 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
41.3.9.5 TWI: Software Reset when a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 41.3.10 Universal Synchronous Asynchronous Receiver Transmitter (USART) 41.3.10.1 USART: CTS in Hardware Handshaking When Hardware Handshaking is used and if CTS goes low near the end of the start bit, a character can be lost.
41.4 AT91SAM7X512 Errata - Rev. A Parts Refer to Section 41.1 “Marking” on page 607. Note: AT91SAM7X512 Revision A chip ID is 0x275C 0A40. 41.4.1 Analog-to-Digital Converter (ADC) 41.4.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 41.4.1.
DRDY already active, GOVRE inactive, previous data stored in LCDR being neither data from channel "y", nor data from channel "x". GOVRE should be set but is not. Problem Fix/Workaround None 41.4.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel "y" at the same instant as an end of conversion on channel "x", EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 41.4.1.
41.4.2 Controller Area Network (CAN) 41.4.2.1 CAN: Low Power Mode and Error Frame If the Low Power Mode is activated while the CAN is generating an error frame, this error frame may be shortened. Problem Fix/Workaround None 41.4.2.2 CAN: Low Power Mode and Pending Transmit Messages No pending transmit messages may be sent once the CAN Controller enters Low-power Mode. Problem Fix/Workaround Check that all messages have been sent by reading the related Flags before entering Low-power Mode. 41.4.
41.4.5.2 PIO: Electrical Characteristics on NRST, PA0-PA30 and PB0-PB26 When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.45 V This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.
Do not disable a channel before completion of one period of the selected clock. 41.4.7 Real Time Timer (RTT) 41.4.7.1 RTT: Possible Event Loss when Reading RTT_SR If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event. Problem Fix/Workaround: The software must handle the RTT event as an interrupt and should not poll RTT_SR. 41.4.8 Serial Peripheral Interface (SPI) 41.4.8.
None. 41.4.8.6 SPI: Bad Serial Clock Generation on 2nd Chip Select Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0. This occurs using SPI with the following conditions: Master mode CPOL = 1 and NCPHA = 0 Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e.
41.4.10 Two-wire Interface (TWI) 41.4.10.1 TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 41.4.10.2 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
41.4.10.5 TWI: Software Reset when a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 41.4.11 Universal Synchronous Asynchronous Receiver Transmitter (USART) 41.4.11.1 USART: CTS in Hardware Handshaking When Hardware Handshaking is used and if CTS goes low near the end of the start bit, a character can be lost.
41.5 AT91SAM7X256/128 Errata - Rev. B Parts Refer to Section 41.1 “Marking” on page 607. Note: AT91SAM7X256 Revision B chip ID is 0x275B 0940. AT91SAM7X128 Revision B chip ID is 0x275A 0740. 41.5.1 Analog-to-Digital Converter (ADC) 41.5.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 41.5.1.
EOC[x] already active, DRDY already active, GOVRE inactive, previous data stored in LCDR being neither data from channel "y", nor data from channel "x". GOVRE should be set but is not. Problem Fix/Workaround None 41.5.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel "y" at the same instant as an end of conversion on channel "x", EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 41.5.1.
41.5.2 Controller Area Network (CAN) 41.5.2.1 CAN: Low Power Mode and Error Frame If the Low Power Mode is activated while the CAN is generating an error frame, this error frame may be shortened. Problem Fix/Workaround None 41.5.2.2 CAN: Low Power Mode and Pending Transmit Messages No pending transmit messages may be sent once the CAN Controller enters Low-power Mode. Problem Fix/Workaround Check that all messages have been sent by reading the related Flags before entering Low-power Mode. 41.5.
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.5 µA 45 µA Problem Fix/Workaround It is recommended to use an external pull-up if needed. 41.5.4.2 PIO: Drive Low NRST, PA0-PA30 and PB0-PB26 When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, driving the I/O with an output impedance higher than 500 ohms may not drive the I/O to a logical zero.
Problem Fix/Workaround: The software must handle the RTT event as an interrupt and should not poll RTT_SR. 41.5.7 Serial Peripheral Interface (SPI) 41.5.7.1 SPI: Bad tx_ready Behavior when CSAAT = 1 and SCBR = 1 If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been transferred in the shifter.
Master Mode CPOL = 1 and NCPHA = 0 Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1 Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is generated on output SPCK during the second transfer.
The data need to be delayed for one bit clock period with an external assembly. In the following schematic, TD, TK and NRST are AT91SAM7X signals, TXD is the delayed data to connect to the device. 41.5.9 Two-wire Interface (TWI) 41.5.9.1 TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 41.5.9.
The user must be sure that received data is read before transmitting any new data. 41.5.9.5 TWI: Software Reset when a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 41.5.10 Universal Synchronous Asynchronous Receiver Transmitter (USART) 41.5.10.1 USART: CTS in Hardware Handshaking When Hardware Handshaking is used and if CTS goes low near the end of the start bit, a character can be lost.
41.6 AT91SAM7X512 Errata - Rev. B Parts Refer to Section 41.1 “Marking” on page 607. Note: AT91SAM7X512 Revision B chip ID is 0x0x275C 0A41. 41.6.1 Analog-to-Digital Converter (ADC) 41.6.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 41.6.1.
DRDY already active, GOVRE inactive, previous data stored in LCDR being neither data from channel "y", nor data from channel "x". GOVRE should be set but is not. Problem Fix/Workaround None 41.6.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel "y" at the same instant as an end of conversion on channel "x", EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 41.6.1.
41.6.2 Controller Area Network (CAN) 41.6.2.1 CAN: Low Power Mode and Error Frame If the Low Power Mode is activated while the CAN is generating an error frame, this error frame may be shortened. Problem Fix/Workaround None 41.6.2.2 CAN: Low Power Mode and Pending Transmit Messages No pending transmit messages may be sent once the CAN Controller enters Low-power Mode. Problem Fix/Workaround Check that all messages have been sent by reading the related Flags before entering Low-power Mode. 41.6.
41.6.5 Peripheral Input/Output (PIO) 41.6.5.1 PIO: Leakage on PB27 - PB30 When PB27, PB28, PB29 or PB30 (the I/O lines multiplexed with the analog inputs) are set as digital inputs with pull-up disabled, the leakage can be 25 µA in worst case and 90 nA in typical case per I/O when the I/O is set externally at low level. Problem Fix/Workaround Set the I/O to VDDIO by internal or external pull-up. 41.6.5.
Problem Fix/Workaround None. 41.6.6.4 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the BITS field of the SPI_CSR0 must be configured in 8 bits, in the same way as the BITS field of the CSRy Register. 41.6.8.5 SPI: Baudrate Set to 1 When Baudrate is set at 1 (i.e.
41.6.9.3 SSC: Transmitter Limitations in Slave Mode If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during data emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is lost. This problem does not exist when generating a periodic synchro. Problem Fix/Workaround The data need to be delayed for one bit clock period with an external assembly.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR. 41.6.10.4 TWI: Possible Receive Holding Register Corruption When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs. Problem Fix/Workaround The user must be sure that received data is read before transmitting any new data. 41.6.
41.7 AT91SAM7X256/128 Errata - Rev. C Parts Refer to Section 41.1 “Marking” on page 607. Note: AT91SAM7X256 Revision C chip ID is 0x275B 0942. AT91SAM7X128 Revision C chip ID is 0x275A 0742. 41.7.1 Boundary Scan 41.7.1.1 BSDL: BSDL File for Rev. B Devices Not Compatible with Rev. C Devices The BSDL file dedicated to Rev. C devices must be used. No other BSDL file is compatible with Rev. C devices. 41.7.2 Embedded Flash Controller (EFC) 41.7.2.
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.5 µA 45 µA Problem Fix/Workaround It is recommended to use an external pull-up if needed. 41.7.4.2 PIO: Drive Low NRST, PA0-PA30 and PB0-PB26 When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, driving the I/O with an output impedance higher than 500 ohms may not drive the I/O to a logical zero.
41.7.7 Serial Peripheral Interface (SPI) 41.7.7.1 SPI: Bad Serial Clock Generation on 2nd Chip Select Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0. This occurs using SPI with the following conditions: Master Mode CPOL = 1 and NCPHA = 0 Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e.
42. Revision History The most recent version appears first in the tables that follow. The acronymn “rfo” indicates change requests made by technical experts during document approval. Version 6120K Change Request Ref. Comments Section 29. ”Two-wire Interface (TWI)” Added bit OVRE to Section 29.6.5 ”TWI Status Register”, Section 29.6.6 ”TWI Interrupt Enable Register”, Section 29.6.7 ”TWI Interrupt Disable Register” and Section 29.6.8 ”TWI Interrupt Mask Register”. Section 16.
Version 6120I Change Request Ref. Comments Ordering Information: Table 40-1, “Ordering Information” The following ordering codes added to the table for MRL C. AT91SAM7X256C-AU 7371 AT91SAM7X256C-CU AT91SAM7X128C-AU AT91SAM7X128C-CU Overview: Section 9.5 ”Debug Unit” rfo “Chip ID Registers” , Chip IDs updated with reference to MRL A, B or C. Product Series Naming Convention: Except for part ordering and library references, AT91 prefix dropped from most nomenclature. rfo AT91SAM7X becomes SAM7X.
Version 6120H Change Request Ref. Comments Overview: Table 3-1, “Signal Description List” footnote added to JTAGSEL, ERASE and TST pin comments. 5064 Section 6.1 ”JTAG Port Pins”, Section 6.2 ”Test Pin” and Section 6.4 ”ERASE Pin”, updated. Section 8.4.3 ”Internal Flash”, updated: “At any time, the Flash is mapped ... if GPNVM bit 2 is set and before the 5850 Remap Command.” Figure 9-1,”System Controller Block Diagram”, RTT is reset by power_on_reset.
Version 6120H (Continued) Comments Change Request Ref. UDP: Section 34.6 ”USB Device Port (UDP) User Interface”, reset value for UDP_RST_EP is 0x000_0000. 5049 Table 34-1, “USB Endpoint Description”, footnote added to Dual-Bank heading. 5150 Section 34.5.2.5 ”Transmit Data Cancellation”, added to datasheet Section 34.6.9 ”UDP Reset Endpoint Register”, added steps to clear endpoints. Electrical Characteristics: Table 38-2, “DC Characteristics”, CMOS conditions added to IO for VOL and VOH.
Version 6120G Change Request Ref. Comments Overview, “Features” , TWI updated to include Atmel TWI compatibility with I2C Standard. 4247 Section 7.4 ”Peripheral DMA Controller” updated with PDC priorities. 4774 Section 10.8 ”Two-wire Interface”, updated. Section 10.11 ”Timer Counter” The TC has Two output compare or one input capture per channel. 4210 Section 10.15 ”Analog-to-Digital Converter” INL and DNL updated.
Version 6120G (Continued) Comments Change Request Ref. SPI, Section 28.6.4 “SPI Slave Mode” on page 254, corrected information on OVRES (SPI_SR) and data read in SPI_RDR. 3943 SSC, Section 31.6.5.1 ”Frame Sync Data”, defined max Frame Sync Data length. 2293 Section 31.6.6.1 ”Compare Functions”, updated with max FSLEN length. TC, 3342 Figure 32-2,”Clock Chaining Selection”, added to Section 32.5 ”Functional Description”. Section 32.
Version 6120G (Continued) Comments Change Request Ref. Electrical Characteristics, Table 38-6, “Power Consumption for Different Modes”; Active mode consumption values updated. Footnote assigned to Flash In standby mode. Footnote assigned to Ultra Low Power mode. 4596/ 4597 Section 38.7 ”ADC Characteristics”, INL and DN updated and Absolute accuracy added to Table 38-18, “Transfer Characteristics”, reference to Data Converter Terminology added below table.
Version 6120F Change Request Ref. Comments AT91SAM7X512 added to product family. “Features” on page 2, “Configuration Summary of the SAM7X512/256/128” on page 4 Global and TFBGA package to Section 4. ”Package”, Section 39. ”SAM7X512/256/128 Mechanical Characteristics” and Section 40. ”AT91SAM7X Ordering Information”. Section 4.1 ”100-lead LQFP Package Outline” and Section 4.3 ”100-ball TFBGA Package Outline” Replace #2724 “...
Version 6120F (Continued) Comments Change Request Ref. DBGU: Corrected references from ice_nreset to Power-on Reset in Figure 26-1 on page 196, Functional Block Diagram, and in FNTRST bit description in Section 26.5.12 “Debug Unit Force NTRST Register” on page 218. 2832 PIO:Section 27.4.4 “Output Control” on page 222, typo corrected 05-346 Section 27.4.1 “Pull-up Resistor Control” on page 221 reference to resistor value removed.
Version 6120F (Continued) Comments Change Request Ref. Section 34. “USB Device Port (UDP)” on page 441: Corrections, improvements, additions and deletions throughout section, new source document. Section 34.5.3.8 ”Sending a Device Remote Wakeup” replaces title “Sending an External Resume. WAKEUP bit shown in interruput registers: Section 34.6.4 on page 450 thru Section 34.6.8 on page 455 3288 RMWUPE, RSMINPR, ESR bits removed from Section 34.6.
Version Comments 6120E 04-Apr-06 Change Request Ref. The following errata have been added: #2455 Section 41.3.3.2 ”EMAC: Possible Event Loss when Reading EMAC_ISR” Section 41.3.3.3 ”EMAC: Possible Event Loss when Reading the Statistics Register Block” Section 41.3.7.3 ”SPI: SPCK Behavior in Master Mode” Section 41.3.4.1 ”PIO: Leakage on PB27 - PB30”: worst case leakage changed to 9 µA 6120D #2605 03-Feb-06 Section 41. ”SAM7X512/256/128 Errata” Device package/product number changed Section 41.3.
Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. Configuration Summary of the SAM7X512/256/128 . . . . . . . . . . . . . 4 2. SAM7X512/256/128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.
9.6 9.7 9.8 9.9 9.10 Periodic Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-time Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIO Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator Controller. . . . . . . . . . . .
16.1 16.2 16.3 16.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer (WDT) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 82 83 85 17. Voltage Regulator Mode Controller (VREG) . . .
25. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . 172 25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Clock Controller . . . . . . . . . . . . . . . . . . . .
face . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 31. Synchronous Serial Controller (SSC) . . . . . . . . . . . . . . . . . . . . . . 337 31.1 31.2 31.3 31.4 31.5 31.6 31.7 31.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . .
36.8 Controller Area Network (CAN) User Interface . . . . . . . . . . . . . . . . . . . . . . 506 37. Ethernet MAC 10/100 (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 37.1 37.2 37.3 37.4 37.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .
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