Datasheet

42
SAM7X Series [SUMMARY DATASHEET]
6120IS–ATARM–14-Nov-13
Revision History
The most recent version appears first in the tables that follow.
The acronymn “rfo” indicates change requests made by technical experts during document approval.
Table 12-2. Revision History
Doc. Rev Comments
Change
Request
Ref.
6120IS Section 12. ”AT91SAM7X Ordering Information”
Added three ordering codes for AT91SAM7X512 MRL B. rfo
6120HS Ordering Information:
Table 12-1, “Ordering Information”, removed ‘MRL C’ column 8194
6120GS Section 12. ”AT91SAM7X Ordering Information”, MRL C parts added to ordering information
Section 9.5 ”Debug Unit”
“Chip ID Registers” , Chip IDs updated with reference to MRL A, B or C.
7371
rfo
Product Series Naming Convention:
Except for part ordering and library references, AT91 prefix dropped from most nomenclature.
AT91SAM7X becomes SAM7X.
6120FS Table 3-1, “Signal Description List” footnote added to JTAGSEL, ERASE and TST pin comments.
Section 6.1 ”JTAG Port Pins”, Section 6.2 ”Test Pin” and Section 6.4 ”ERASE Pin”, updated.
5064
Section 8.4.3 ”Internal Flash”, updated: “At any time, the Flash is mapped... if GPNVM bit 2 is set and
before the Remap Command.”
5850
Figure 9-1,”System Controller Block Diagram”, RTT is reset by power_on_reset. 5223
”Features”, ”Debug Unit (DBGU)”, added ”Mode for General Purpose 2-wire UART Serial
Communication”
5846
Section 12. ”AT91SAM7X Ordering Information”, MRL B parts added to ordering information. 6064
6120ES “Features” ,TWI updated to include Atmel TWI compatibility with I2C Standard.
Section 10.8 ”Two-wire Interface”, updated.
Section 7.4 ”Peripheral DMA Controller”, added PDC priority list.
Section 10.11 ”Timer Counter”, The TC has Two output compare or one input capture per channel.
Section 10.15 ”Analog-to-Digital Converter”, INL and DNL updated.
4247
4774
4210
4007
6120DS
Added AT91SAM7X512 to product family.“Features” on page 2 and global
Reformatted Memories Section 8. “Memories” on page 17.
Reordered sub sections in Peripherals Section 10. “Peripherals” on page 30
Consolidated Memory Mapping in Figure 8-1 on page 18.
Added TFBGA information Section 4.3 “100-ball TFBGA Package Outline” on page 10.
added LQFP and TFBGA package drawings Section 11. on page 38.
2723
2728
System Controller block diagram Figure 9-1 on page 24, “ice_nreset” signals changed to
“power_on_reset”.
Section 10.1 ”User Interface” User Peripherals are mapped between 0xF000 0000 and 0XFFFF EFFF.
Table 10-1 on page 30 SYSIRQ changed to SYSC in “Peripheral Identifiers”
rfo review