Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 16/32-Bit 55 MHz I/O number 62

This is a summary document.

The complete document is

available on the Atmel website

at www.atmel.com.

6120IS–ATARM–14-Nov-13

Description

The Atmel SAM7X512/256/128 is a highly-integrated Flash microcontroller based on

the 32-bit ARM

RISC processor. It features 512/256/128 Kbytes of high-speed Flash

and 128/64/32 Kbytes of SRAM, a large set of peripherals, including an 802.3 Ethernet

MAC, and a CAN controller. A complete set of system functions minimizes the number

of external components.

The embedded Flash memory can be programmed in-system via the JTAG-ICE

interface or via a parallel interface on a production programmer prior to mounting. Built-

in lock bits and a security bit protect the firmware from accidental overwrite and

preserve its confidentiality.

The SAM7X512/256/128 system controller includes a reset controller capable of

managing the power-on sequence of the microcontroller and the complete system.

Correct device operation can be monitored by a built-in brownout detector and a

watchdog running off an integrated RC oscillator.

By combining the ARM7TDMI

processor with on-chip Flash and SRAM, and a wide

range of peripheral functions, including USART, SPI, CAN controller, Ethernet MAC,

Timer Counter, RTT and analog-to-digital converters on a monolithic chip, the

SAM7X512/256/128 is a powerful device that provides a flexible, cost-effective solution

to many embedded control applications requiring communication over Ethernet, wired

CAN and ZigBee

wireless networks.

ARM-based Flash MCU

SAM7X512 / SAM7X256 / SAM7X128

SUMMARY DATASHEET

Summary of content (44 pages)

PAGE 1
ARM-based Flash MCU SAM7X512 / SAM7X256 / SAM7X128 SUMMARY DATASHEET Description The Atmel SAM7X512/256/128 is a highly-integrated Flash microcontroller based on the 32-bit ARM® RISC processor. It features 512/256/128 Kbytes of high-speed Flash and 128/64/32 Kbytes of SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, and a CAN controller. A complete set of system functions minimizes the number of external components.
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Features  Incorporates the ARM7TDMI ARM Thumb® Processor  High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set  Leader in MIPS/Watt  EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support   Internal High-speed Flash  512 Kbytes (SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane)  256 Kbytes (SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane)  128 Kbytes (SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane)  Single
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 Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output  Thirteen Peripheral DMA Controller (PDC) Channels  One USB 2.0 Full Speed (12 Mbits per second) Device Port  On-chip Transceiver, 1352-byte Configurable Integrated FIFOs  One Ethernet MAC 10/100 base-T   Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive  One Part 2.0A and Part 2.
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1. Configuration Summary of the SAM7X512/256/128 The SAM7X512, SAM7X256 and SAM7X128 differ only in memory sizes. Table 1-1 summarizes the configurations of the three devices. Table 1-1.
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SAM7X512/256/128 Block Diagram SAM7X512/256/128 Block Diagram TDI TDO TMS TCK ICE JTAG SCAN ARM7TDMI Processor JTAGSEL 1.
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3. Signal Description Table 3-1.
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Table 3-1.
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Table 3-1. Signal Name ETXER ERXDV ECRSDV ERX0 - ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Note: Signal Description List (Continued) Function Transmit Coding Error Receive Data Valid Carrier Sense and Data Valid Receive Data Receive Error Carrier Sense Collision Detected Management Data Clock Management Data Input/Output Force 100 Mbits/sec.
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4. Package The SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS-compliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical description is given in the Mechanical Characteristics section. Figure 4-1. 100-lead LQFP Package Outline (Top View) 75 51 76 50 100 26 1 4.2 25 100-lead LQFP Pinout Table 4-1.
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4.3 100-ball TFBGA Package Outline Figure 4-2 shows the orientation of the 100-ball TFBGA package. A detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-2. 100-ball TFBGA Package Outline (Top View) TOP VIE 10 9 8 7 6 5 4 3 2 1 BALL A1 4.
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5. Power Considerations 5.1 Power Supplies The SAM7X512/256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are:  VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal. In order to decrease current consumption, if the voltage regulator and the ADC are not used, VDDIN, ADVREF, AD4, AD5, AD6 and AD7 should be connected to GND.
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Figure 5-1. 3.3V System Single Power Supply Schematic VDDFLASH Power Source ranges from 4.5V USB to 18V DC/DC Con erter VDDIO VDDIN Voltage Regulator 3.
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6. I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND.
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6.6 I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA.
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7. Processor and Architecture 7.1 ARM7TDMI Processor  RISC processor based on ARMv4T Von Neumann architecture    7.2 Two instruction sets  ARM high-performance 32-bit instruction set  Thumb high code density 16-bit instruction set Three-stage pipeline architecture  Instruction Fetch (F)  Instruction Decode (D)  Execute (E) Debug and Test Features    7.3 Runs at up to 55 MHz, providing 0.
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 7.
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8. Memories 8.
PAGE 18
Figure 8-1.
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8.4 Memory Mapping 8.4.1 Internal SRAM  The SAM7X512 embeds a high-speed 128-Kbyte SRAM bank.  The SAM7X256 embeds a high-speed 64-Kbyte SRAM bank.  The SAM7X128 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.4.2 Internal ROM The SAM7X512/256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000.
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Figure 8-3. Internal Memory Mapping with GPNVM Bit 2 = 1 x 0x000F FFFF Flash Before Remap SRAM After Remap 1 M Bytes x Internal FLASH 1 M Bytes Internal SRAM 1 M Bytes Internal ROM 1 M Bytes 0x001F FFFF x 256M Bytes 0x002F FFFF 0x0030 0000 0x003F FFFF 0x0040 0000 Undefined Areas Abort 252 M Bytes 0x0FFF FFFF 8.5 Embedded Flash 8.5.1 Flash Overview  The Flash of the SAM7X512 is organized in two banks (dual plane) of 1024 pages of 256 bytes.
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8.5.3 8.5.3.1 Lock Regions SAM7X512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The SAM7X512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 32 NVM bits are software programmable through both of the EFC User Interfaces.
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 8.5.6 The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default. Calibration Bits Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
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9. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 9-1 on page 24 shows the System Controller Block Diagram. Figure 8-1 on page 18 shows the mapping of the User Interface of the System Controller peripherals.
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Figure 9-1. System Controller Block Diagram System Controller Boundary Scan TAP Controller jtag_nreset nirq irq0-irq1 Advanced Interrupt Controller fiq periph_irq[2..
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9.1 9.1.1 Reset Controller  Based on one power-on reset cell and one brownout detector  Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset  Controls the internal resets and the NRST pin output  Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. Brownout Detector and Power-on Reset The SAM7X512/256/128 embeds one brownout detection circuit and a power-on reset cell.
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9.2 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics:  RC Oscillator ranges between 22 KHz and 42 KHz  Main Oscillator frequency ranges between 3 and 20 MHz  Main Oscillator can be bypassed  PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2.
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9.3 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide:  the Processor Clock PCK  the Master Clock MCK  the USB Clock UDPCK  all the peripheral clocks, independently controllable  four programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device.
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 Protect Mode  Fast Forcing      Comprises:  One two-pin UART  One Interface for the Debug Communication Channel (DCC) support  One set of Chip ID Registers  One Interface providing ICE Access Prevention Two-pin UART  USART-compatible User Interface  Programmable Baud Rate Generator  Parity, Framing and Overrun Error  Automatic Echo, Local Loopback and Remote Loopback Channel Modes Debug Communication Channel Support   9.8 9.
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 9.10  Half a clock period glitch filter  Multi-drive option enables driving in open drain  Programmable pull-up on each I/O line  Pin data status register, supplies visibility of the level on the pin at any time Synchronous output, provides Set and Clear of several I/O lines in a single write Voltage Regulator Controller The voltage regulator controller selects the power mode of the Voltage Regulator between normal mode (bit 0 is cleared) or standby mode (bit 0 is set).
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10. Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 Mbytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in Figure 8-1 on page 18. 10.2 Peripheral Identifiers The SAM7X512/256/128 embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the SAM7X512/256/128.
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10.3 Peripheral Multiplexing on PIO Lines The SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller.
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10.4 PIO Controller A Multiplexing Table 10-2.
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10.5 PIO Controller B Multiplexing Table 10-3.
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10.6 10.7 Ethernet MAC  DMA Master on Receive and Transmit Channels  Compatible with IEEE Standard 802.
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10.9 USART  Programmable Baud Rate Generator  5- to 9-bit full-duplex synchronous or asynchronous serial communications  1, 1.
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 Five internal clock inputs, as defined in Table 10-4 Table 10-4. Timer Counter Clocks Assignment TC Clock input Clock TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 MCK/1024  Two multi-purpose input/output signals  Two global registers that act on all three TC channels 10.
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 16-bit internal timer for time stamping and network synchronization  Programmable reception buffer length up to 8 mailbox objects  Priority management between transmission mailboxes  Autobaud and listening mode  Low power mode and programmable wake-up on bus activity or by the application  Data, remote, error and overload frame handling 10.15 Analog-to-Digital Converter  8-channel ADC  10-bit 384 K samples/sec.
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11. Package Drawings 11.1 100-lead LQFP Package Figure 11-1.
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Table 11-1. 100-lead LQFP Package Dimensions Millimeter Symbol Min Nom A Inch Max Min Nom 1.60 A1 0.05 A2 1.35 1.40 0.15 0.002 1.45 0.053 0.006 0.055 D 16.00 BSC 0.630 BSC D1 14.00 BSC 0.551 BSC E 16.00 BSC 0.630 BSC E1 14.00 BSC 0.551 BSC R2 0.08 R1 0.08 0.20 0.003 0° θ1 0° θ2 11° 12° 13° θ3 11° 12° 13° c 0.09 0.20 0.004 L 0.45 0.60 0.75 0.018 0.20 b 0.17 e 3.5° 7° 0° 0.008 3.5° 7° 11° 12° 13° 11° 12° 13° 0.024 0.030 0° 1.
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11.2 100-ball TFBGA Package Figure 11-2.
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12. AT91SAM7X Ordering Information Table 12-1. Ordering Information MRL A Ordering Code MRL B Ordering Code AT91SAM7X512-AU AT91SAM7X512B-AU – AT91SAM7X512B-AUR AT91SAM7X512-CU AT91SAM7X512B-CU AT91SAM7X256-AU AT91SAM7X256B-AU AT91SAM7X256C-AU LQFP 100 AT91SAM7X256-CU AT91SAM7X256B-CU AT91SAM7X256C-CU TFBGA 100 AT91SAM7X128-AU AT91SAM7X128B-AU AT91SAM7X128C-AU LQFP 100 AT91SAM7X128-CU AT91SAM7X128B-CU AT91SAM7X128C-CU TFBGA 100 Note: 1.
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Revision History The most recent version appears first in the tables that follow. The acronymn “rfo” indicates change requests made by technical experts during document approval. Table 12-2. Doc. Rev 6120IS 6120HS 6120GS 6120FS 6120ES 6120DS Revision History Comments Section 12. ”AT91SAM7X Ordering Information” Added three ordering codes for AT91SAM7X512 MRL B. Ordering Information: Table 12-1, “Ordering Information”, removed ‘MRL C’ column Section 12.
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Table 12-2. Doc. Rev 6120CS Revision History Comments Update to product functionalities including changes to “Features” on page 2, Figure 2-1 on page 5, Section 9.5 “Debug Unit” on page 28 and to Peripheral mapping. Updated PLL output range max value in Section 9.2 “Clock Generator” on page 26. Updated information in Section 5.1 “Power Supplies” on page 11. Updated ordering information in “Ordering Information” on page 41. Change Request Ref.
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