Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LFBGA 144 (10x10) 16/32-Bit 55 MHz I/O number 88

NOTE: This is a summary document.

The complete document is available on

the Atmel website at www.atmel.com.

Features

• Incorporates the ARM7TDMI

ARM

Thumb

Processor

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– EmbeddedICE

™

In-circuit Emulation, Debug Communication Channel Support

• Internal High-speed Flash

– 512 Kbytes, Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes Dual

Plane (SAM7SE512)

– 256 Kbytes (SAM7SE256) Organized in One Bank of 1024 Pages of 256 Bytes

Single Plane (SAM7SE256)

– 32 Kbytes (SAM7SE32) Organized in One Bank of 256 Pages of 128 Bytes Single

Plane (SAM7SE32)

– Single Cycle Access at Up to 30 MHz in Worst Case Conditions

– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed

– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms

– 10,000 Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,

Flash Security Bit

– Fast Flash Programming Interface for High Volume Production

• 32 Kbytes (SAM7SE512/256) or 8 Kbytes (SAM7SE32) of Internal

High-speed SRAM, Single-cycle Access at Maximum Speed

• One External Bus Interface (EBI)

– Supports SDRAM, Static Memory, Glueless Connection to CompactFlash

and

ECC-enabled NAND Flash

• Memory Controller (MC)

– Embedded Flash Controller

– Memory Protection Unit

– Abort Status and Misalignment Detection

• Reset Controller (RSTC)

– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout

Detector

– Provides External Reset Signal Shaping and Reset Source Status

• Clock Generator (CKGR)

– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL

• Power Management Controller (PMC)

– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and

Idle Mode

– Three Programmable External Clock Signals

• Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources

– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt

Protected

• Debug Unit (DBGU)

– Two-wire UART and Support for Debug Communication Channel interrupt,

Programmable ICE Access Prevention

– Mode for General Purpose Two-wire UART Serial Communication

• Periodic Interval Timer (PIT)

– 20-bit Programmable Counter plus 12-bit Interval Counter

• Windowed Watchdog (WDT)

– 12-bit key-protected Programmable Counter

AT91SAM

ARM-based

Flash MCU

SAM7SE512

SAM7SE256

SAM7SE32

Summary

6222GS–ATARM–6-Sep-11

Summary of content (47 pages)

PAGE 1
Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash – 512 Kbytes, Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes Dual Plane (SAM7SE512) – 256 Kbytes (SAM7SE256) Organized in One Bank of 1024 Pages of 256 Bytes Single Plane (SAM7SE256) – 32 Kbytes (SAM7SE32)
PAGE 2
• • • • • • • • • • • • • • • • • 2 – Provides Reset or Interrupt Signals to the System – Counter May Be Stopped While the Processor is in Debug State or in Idle Mode Real-time Timer (RTT) – 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator Three Parallel Input/Output Controllers (PIO) – Eighty-eight Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resis
PAGE 3
SAM7SE512/256/32 Summary 1. Description Atmel's SAM7SE Series is a member of its Smart ARM Microcontroller family based on the 32bit ARM7™ RISC processor and high-speed Flash memory. • SAM7SE512 features a 512-Kbyte high-speed Flash and a 32 Kbyte SRAM. • SAM7SE256 features a 256-Kbyte high-speed Flash and a 32 Kbyte SRAM. • SAM7SE32 features a 32-Kbyte high-speed Flash and an 8 Kbyte SRAM. It also embeds a large set of peripherals, including a USB 2.
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2. Block Diagram Figure 2-1. SAM7SE512/256/32 Block Diagram Signal Description ICE TDI TDO TMS TCK ARM7TDMI Processor JTAG SCAN JTAGSEL TST 1.
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SAM7SE512/256/32 Summary 3. Signal Description Table 3-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDIN Voltage Regulator and ADC Power Supply Input Power 3V to 3.6V VDDOUT Voltage Regulator Output Power 1.85V VDDFLASH Flash and USB Power Supply Power 3V to 3.6V VDDIO I/O Lines Power Supply Power 3V to 3.6V or 1.65V to 1.95V VDDCORE Core Power Supply Power 1.65V to 1.95V VDDPLL PLL Power 1.65V to 1.
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Table 3-1.
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SAM7SE512/256/32 Summary Table 3-1.
PAGE 8
Table 3-1.
PAGE 9
SAM7SE512/256/32 Summary 4. Package The SAM7SE512/256/32 is available in: • 20 x 14 mm 128-lead LQFP package with a 0.5 mm lead pitch. • 10x 10 x 1.4 mm 144-ball LFBGA package with a 0.8 mm lead pitch 4.1 128-lead LQFP Package Outline Figure 4-1 shows the orientation of the 128-lead LQFP package and a detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-1.
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4.2 128-lead LQFP Pinout Table 4-1.
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SAM7SE512/256/32 Summary 4.3 144-ball LFBGA Package Outline Figure 4-2 shows the orientation of the 144-ball LFBGA package and a detailed mechanical description is given in the Mechanical Characteristics section. Figure 4-2.
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4.4 144-ball LFBGA Pinout Table 4-2.
PAGE 13
SAM7SE512/256/32 Summary 5. Power Considerations 5.1 Power Supplies The SAM7SE512/256/32 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal. • VDDOUT pin. It is the output of the 1.8V voltage regulator. • VDDIO pin. It powers the I/O lines; two voltage ranges are supported: – from 3.0V to 3.
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• One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 5.4 Typical Powering Schematics The SAM7SE512/256/32 supports a 3.3V single supply mode. The internal regulator input connected to the 3.
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SAM7SE512/256/32 Summary 6. /O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ.
PAGE 16
6.5 SDCK Pin The SDCK pin is dedicated to the SDRAM Clock and is an output-only without pull-up. Maximum Output Frequency of this pad is 48 MHz at 3.0V and 25 MHz at 1.65V with a maximum load of 30 pF. 6.6 PIO Controller lines All the I/O lines PA0 to PA31, PB0 to PB31, PC0 to PC23 integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. Typical pull-up value is 100 kΩ.
PAGE 17
SAM7SE512/256/32 Summary 7. Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs at up to 55 MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V) • Two instruction sets – ARM® high-performance 32-bit instruction set – Thumb® high code density 16-bit instruction set • Three-stage pipeline architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 7.
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– Individually programmable size between 1K Byte and 1M Byte – Individually programmable protection against write and/or user access – Peripheral protection against write and/or user access • Embedded Flash Controller – Embedded Flash interface, up to three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Inte
PAGE 19
SAM7SE512/256/32 Summary • Multiple device adaptability – Compliant with LCD Module – Compliant with PSRAM in synchronous operations – Programmable Setup Time Read/Write – Programmable Hold Time Read/Write • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time 7.
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7.
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SAM7SE512/256/32 Summary 8.
PAGE 22
Figure 8-1.
PAGE 23
SAM7SE512/256/32 Summary A first level of address decoding is performed by the Memory Controller, i.e., by the implementation of the Advanced System Bus (ASB) with additional features. Decoding splits the 4G bytes of address space into 16 areas of 256M bytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NC0 to NCS7. The area 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M byte of internal memory area.
PAGE 24
Figure 8-2. Internal Memory Mapping with GPNVM Bit 2 = 0 (default) 0x0000 0000 0x000F FFFF ROM Before Remap SRAM After Remap 1 M Bytes 0x0010 0000 Internal FLASH 1 M Bytes Internal SRAM 1 M Bytes Internal ROM 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 0x003F FFFF 0x0040 0000 Undefined Areas (Abort) 252 M Bytes 0x0FFF FFFF Figure 8-3.
PAGE 25
SAM7SE512/256/32 Summary The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions. 8.1.2.2 Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB.
PAGE 26
The security bit can only be enabled through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1 and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 200 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation.
PAGE 27
SAM7SE512/256/32 Summary 8.1.4 SAM-BA® Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port. • Communication via the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-detection. • Communication via the USB Device Port is limited to an 18.432 MHz crystal.
PAGE 28
9. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 9-1 on page 29 shows the System Controller Block Diagram. Figure 8-1 on page 22 shows the mapping of the User Interface of the System Controller peripherals.
PAGE 29
SAM7SE512/256/32 Summary Figure 9-1. System Controller Block Diagram jtag_nreset System Controller Boundary Scan TAP Controller nirq irq0-irq1 nfiq Advanced Interrupt Controller fiq periph_irq[2..
PAGE 30
9.1 Reset Controller • Based on one power-on reset cell and a double brownout detector • Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset • Controls the internal resets and the NRST pin output • Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. 9.1.1 Brownout Detector and Power On Reset The SAM7SE512/256/32 embeds one brownout detection circuit and a power-on reset cell.
PAGE 31
SAM7SE512/256/32 Summary • Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 220 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2. Clock Generator Block Diagram Clock Generator XIN Embedded RC Oscillator Slow Clock SLCK Main Oscillator Main Clock MAINCK PLL and Divider PLL Clock PLLCK XOUT PLLRC Status Control Power Management Controller 9.
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Figure 9-3. Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK PCK int Idle Mode Prescaler /1,/2,/4,...,/64 MCK Peripherals Clock Controller periph_clk[2..14] ON/OFF Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 USB Clock Controller ON/OFF PLLCK 9.4 Divider /1,/2,/4 pck[0..
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SAM7SE512/256/32 Summary 9.
PAGE 34
• Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).
PAGE 35
SAM7SE512/256/32 Summary 10. Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of the address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 22. 10.2 Peripheral Identifiers The SAM7SE512/256/32 embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the SAM7SE512/256/32.
PAGE 36
10.3 Peripheral Multiplexing on PIO Lines The SAM7SE512/256/32 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. PIO Controller A and B control 32 lines; PIO Controller C controls 24 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller.
PAGE 37
SAM7SE512/256/32 Summary 10.4 PIO Controller A Multiplexing Table 10-2.
PAGE 38
10.5 PIO Controller B Multiplexing Table 10-3.
PAGE 39
SAM7SE512/256/32 Summary 10.6 PIO Controller C Multiplexing Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A Peripheral B PC0 D0 PC1 D1 PC2 D2 PC3 D3 PC4 D4 PC5 D5 PC6 D6 PC7 D7 PC8 D8 RTS1 PC9 D9 DTR1 PC10 D10 PCK0 PC11 D11 PCK1 PC12 D12 PCK2 PC13 D13 PC14 D14 NPCS1 PC15 D15 NCS3/NANDCS PC16 A18 NWAIT PC17 A19 NANDOE PC18 A20 NANDWE PC19 A21/NANDALE PC20 A22/REG/NANDCLE NWR0/NWE/CFWE PC22 NRD/CFOE 10.
PAGE 40
– 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays per chip select, between consecutive transfers and between clock and data – Programmable delay between consecutive transfers – Selectable mode fault detection – Maximum frequency at up to Master Clock 10.
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SAM7SE512/256/32 Summary • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.
PAGE 42
10.13 USB Device Port • USB V2.0 full-speed compliant,12 Mbits per second. • Embedded USB V2.0 full-speed transceiver • Embedded 2688-byte dual-port RAM for endpoints • Eight endpoints – Endpoint 0: 64bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Endpoint 4 and 5: 512 bytes ping-pong – Endpoint 6 and 7: 64 bytes ping-pong – Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints • Suspend/resume logic • Integrated Pull-up on DDP 10.
PAGE 43
SAM7SE512/256/32 Summary 11. Package Drawings Figure 11-1.
PAGE 44
Figure 11-2.
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SAM7SE512/256/32 Summary 12. Ordering Information Table 12-1.
PAGE 46
Revision History Doc. Rev Change Request Ref. Comments First issue 6222AS Revised Memories with condensed mapping. Added Package Outlines and 144-ball LFBGA pin and ordering information. #2709 6222BS Section 12. “Ordering Information” on page 45 ordering information code reference changed #3699 #3826 6222CS Section 6.1 ”JTAG Port Pins”, Section 6.3 ”Reset Pin”, Section 6.5 ”SDCK Pin”, removed statement: “not 5V tolerant” Section 7.
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