Datasheet

31
6222GS–ATARM–6-Sep-11
SAM7SE512/256/32 Summary
• Main Oscillator frequency ranges between 3 and 20 MHz
• Main Oscillator can be bypassed
• PLL output ranges between 80 and 220 MHz
It provides SLCK, MAINCK and PLLCK.
Figure 9-2. Clock Generator Block Diagram
9.3 Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide:
• the Processor Clock PCK
• the Master Clock MCK
• the USB Clock UDPCK
• all the peripheral clocks, independently controllable
• three programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre-
quency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing
reduced power consumption while waiting for an interrupt.
Power
Management
Controller
XIN
XOUT
PLLRC
Slow Clock
SLCK
Main Clock
MAINCK
PLL Clock
PLLCK
Control
Status
Embedded
RC
Oscillator
Main
Oscillator
PLL and
Divider
Clock Generator