Datasheet

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6222GS–ATARM–6-Sep-11
SAM7SE512/256/32 Summary
A first level of address decoding is performed by the Memory Controller, i.e., by the implementa-
tion of the Advanced System Bus (ASB) with additional features.
Decoding splits the 4G bytes of address space into 16 areas of 256M bytes. The areas 1 to 8 are
directed to the EBI that associates these areas to the external chip selects NC0 to NCS7. The
area 0 is reserved for the addressing of the internal memories, and a second level of decoding
provides 1M byte of internal memory area. The area 15 is reserved for the peripherals and pro-
vides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
8.1 Embedded Memories
8.1.1 Internal Memories
8.1.1.1 Internal SRAM
The SAM7SE512/256 embeds a high-speed 32-Kbyte SRAM bank. The SAM7SE32 embeds a
high-speed 8-Kbyte SRAM bank. After reset and until the Remap Command is performed, the
SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes avail-
able at address 0x0.
8.1.1.2 Internal ROM
The SAM7SE512/256/32 embeds an Internal ROM. At any time, the ROM is mapped at address
0x30 0000. The ROM contains the FFPI and the SAM-BA boot program.
8.1.1.3 Internal Flash
• The SAM7SE512 features two banks of 256 Kbytes of Flash.
• The SAM7SE256 features one bank of 256 Kbytes of Flash.
• The SAM7SE32 features one bank of 32 Kbytes of Flash.
At any time, the Flash is mapped to address 0x0010 0000.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
This GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.
Setting the GPNVM bit 2 selects the boot from the Flash, clearing it selects the boot from the
ROM. Asserting ERASE clears the GPNVM bit 2 and thus selects the boot from the ROM by
default.