Datasheet

19
6222GS–ATARM–6-Sep-11
SAM7SE512/256/32 Summary
• Multiple device adaptability
– Compliant with LCD Module
– Compliant with PSRAM in synchronous operations
– Programmable Setup Time Read/Write
– Programmable Hold Time Read/Write
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
7.6 SDRAM Controller
• Numerous configurations supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
• Programming facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
• Energy-saving capabilities
– Self-refresh, and Low-power Modes supported
• Error detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• Latency is set to two clocks (CAS Latency of 1, 3 Not Supported)
• Auto Precharge Command not used
• Mobile SDRAM supported (except for low-power extended mode and deep power-down
mode)
7.7 Error Corrected Code Controller
• Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select
• Single bit error correction and 2-bit Random detection.
• Automatic Hamming Code Calculation while writing
– ECC value available in a register
• Automatic Hamming Code Calculation while reading
– Error Report, including error flag, correctable error flag and word address being
detected erroneous
– Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte
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