Datasheet

49
SAM7S Series [DATASHEET]
6175KS–ATARM–25-Oct-12
6175GS
“Features” ,“Debug Unit (DBGU)” updated with “Mode for General Purpose 2-wire UART Serial
Communication”
Section 7.4 ”Peripheral DMA Controller”, added list of PDC priorities.
Section 9. ”System Controller”, Figure 9-1 and Figure 9-2 RTT is reset by “power_on_reset”.
Section 9.1.1 ”Brownout Detector and Power-on Reset”, fourth paragraph reduced.
Section 9.5 ”Debug Unit”, the list; Section l ”Chip ID Registers”, chip IDs updated, added SAM7S32 Rev
B and SAM7S64 Rev B to the list.
Section 12. ”SAM7S Ordering Information”, Updated product ordering information by MRL A and MRL B
versions.
5846
5913
5224
5685
rfo
6175HS
Section 6.2 ”Test Pin”, added to SAM-BA Boot recovery procedure, a power cycle of the board is
mandatory.
Section 8.10 ”SAM-BA Boot Assistant”, added to SAM-BA Boot recovery procedure, a power cycle of the
board is mandatory.
6068
6175IS
Section 9.5 ”Debug Unit”, Chip ID Registers list updated.
MRL C column added to Table 12-1, “SAM7S Series Ordering Information”.
7185
6175JS
Product Series Naming Convention
Except for part ordering and library references, AT91 prefix dropped from most nomenclature.
AT91SAM7S becomes SAM7S.
Debug Unit:
“Chip ID Registers” on page 31, Chip ID is 0x270B0A4F for AT91SAM7S512 Rev B
rfo
7945
6175KS
Section 9.5 ”Debug Unit”, Chip ID Registers list updated. Added Chip ID for SAM7S128 Rev D and
SAM7S256 Rev D
Table 12-1, “SAM7S Series Ordering Information”.Added SAM7S128 Rev D and SAM7S256 Rev D
8380/8467
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