Datasheet

SAM7S Series [DATASHEET]

6175KS–ATARM–25-Oct-12

z One set of Chip ID Registers

z One Interface providing ICE Access Prevention

z Two-pin UART

z Implemented features are compatible with the USART

z Programmable Baud Rate Generator

z Parity, Framing and Overrun Error

z Automatic Echo, Local Loopback and Remote Loopback Channel Modes

z Debug Communication Channel Support

z Offers visibility of COMMRX and COMMTX signals from the ARM Processor

z Chip ID Registers

z Identification of the device revision, sizes of the embedded memories, set of peripherals

z Chip ID is 0x270B0A40 for AT91SAM7S512 Rev A

z Chip ID is 0x270B0A4F for AT91SAM7S512 Rev B

z Chip ID is 0x270D0940 for AT91SAM7S256 Rev A

z Chip ID is 0x270B0941 for AT91SAM7S256 Rev B

z Chip ID is 0x270B0942 for AT91SAM7S256 Rev C

z Chip ID is TBD for AT91SAM7S256 Rev D

z Chip ID is 0x270C0740 for AT91SAM7S128 Rev A

z Chip ID is 0x270A0741 for AT91SAM7S128 Rev B

z Chip ID is 0x270A0742 for AT91SAM7S128 Rev C

z Chip ID is TBD for AT91SAM7S128 Rev D

z Chip ID is 0x27090540 for AT91SAM7S64 Rev A

z Chip ID is 0x27090543 for AT91SAM7S64 Rev B

z Chip ID is 0x27090544 for AT91SAM7S64 Rev C

z Chip ID is 0x27080342 for AT91SAM7S321 Rev A

z Chip ID is 0x27080340 for AT91SAM7S32 Rev A

z Chip ID is 0x27080341 for AT91SAM7S32 Rev B

z Chip ID is 0x27050241 for AT9SAM7S161 Rev A

z Chip ID is 0x27050240 for AT91SAM7S16 Rev A

Note: Refer to the errata section of the datasheet for updates on chip ID.

9.6 Periodic Interval Timer

z 20-bit programmable counter plus 12-bit interval counter

9.7 Watchdog Timer

z 12-bit key-protected Programmable Counter running on prescaled SCLK

z Provides reset or interrupt signals to the system

z Counter may be stopped while the processor is in debug state or in idle mode

9.8 Real-time Timer

z 32-bit free-running counter with alarm running on prescaled SCLK

z Programmable 16-bit prescaler for SLCK accuracy compensation