Datasheet

30
SAM7S Series [DATASHEET]
6175KS–ATARM–25-Oct-12
Figure 9-4. Power Management Controller Block Diagram
9.4 Advanced Interrupt Controller
z Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
z Individually maskable and vectored interrupt sources
z Source 0 is reserved for the Fast Interrupt Input (FIQ)
z Source 1 is reserved for system peripherals RTT, PIT, EFC, PMC, DBGU, etc.)
z Other sources control the peripheral interrupts or external interrupts
z Programmable edge-triggered or level-sensitive internal sources
z Programmable positive/negative edge-triggered or high/low level-sensitive external sources
z 8-level Priority Controller
z Drives the normal interrupt of the processor
z Handles priority of the interrupt sources
z Higher priority interrupts can be served during service of lower priority interrupt
z Vectoring
z Optimizes interrupt service routine branch and execution
z One 32-bit vector register per interrupt source
z Interrupt vector register reads the corresponding current interrupt vector
z Protect Mode
z Easy debugging by preventing automatic operations
z Fast Forcing
z Permits redirecting any interrupt source on the fast interrupt
z General Interrupt Mask
z Provides processor synchronization on events without triggering an interrupt
9.5 Debug Unit
z Comprises:
z One two-pin UART
z One Interface for the Debug Communication Channel (DCC) support
MCK
periph_clk[2..14]
int
UDPCK
usb_suspend
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,...,/64
PCK
Processor
Clock
Controller
Idle Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
USB Clock Controller
ON/OFF
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
PLLCK
Divider
/1,/2,/4
pck[0..2]