Datasheet

581
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7
(Receive Start Selection), two Periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabilization. Figure
37-16 illustrates Min and Max accesses for SSC0. The same applies for SSC1, SSC4, and SSC7, SSC10 and SSC13.
3. 3.3V domain: V
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 40 pF.
4. 1.8V domain: V
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 20 pF.
5. t
CPMCK
: Master Clock period in ns
Figure 37-16. Min and Max access time of output signals
SSC
7
(1)
TK edge to TF/TD (TK input, TF input)
3.3V domain 6 (+3*t
CPMCK
)
(1)(2)
29.5 (+3*t
CPMCK
)
(1)(2)
ns
1.8V domain 10 (+3*t
CPMCK
)
(1)(2)
56 (+3*t
CPMCK
)
(1)(2)
ns
Receiver
SSC
8
RF/RD setup time before RK edge (RK input)
3.3V domain 0 ns
1.8V domain 0 ns
SSC
9
RF/RD hold time after RK edge (RK input)
3.3V domain t
CPMCK
ns
1.8V domain t
CPMCK
ns
SSC
10
RK edge to RF (RK input)
3.3V domain 6
(2)
27
(2)
ns
1.8V domain 10.5
(2)
58
(2)
ns
SSC
11
RF/RD setup time before RK edge (RK output)
3.3V domain 26 - t
CPMCK
ns
1.8V domain 56.5 - t
CPMCK
ns
SSC
12
RF/RD hold time after RK edge (RK output)
3.3V domain t
CPMCK
- 10 ns
1.8V domain t
CPMCK
- 5.5 ns
SSC
13
RK edge to RF (RK output)
3.3V domain 0
(2)
4
(2)
ns
1.8V domain 0
(2)
12
(2)
ns
Table 37-23. SSC Timings (Continued)
Symbol Parameter Conditions Min Max Units
TK (CKI =0)
TF/TD
SSC
0min
TK (CKI =1)
SSC
0max