Datasheet

574
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
37.9 ADC Characteristics
Notes: 1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for
conversion.
2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for
conversion.
The user can drive ADC input with impedance up to:
•Z
OUT
≤ (SHTIM -470) x 10 in 8-bit resolution mode
•Z
OUT
≤ (SHTIM -589) x 7.69 in 10-bit resolution mode
with SHTIM (Sample and Hold Time register) expressed in ns and Z
OUT
expressed in ohms.
Table 37-18. Channel Conversion Time and ADC Clock
Parameter Conditions Min Typ Max Units
ADC Clock Frequency 10-bit resolution mode 5 MHz
ADC Clock Frequency 8-bit resolution mode 8 MHz
Startup Time Return from Idle Mode 20 µs
Track and Hold Acquisition Time 600 ns
Conversion Time ADC Clock = 5 MHz 2 µs
Conversion Time ADC Clock = 8 MHz 1.25 µs
Throughput Rate ADC Clock = 5 MHz 384
(1)
kSPS
Throughput Rate ADC Clock = 8 MHz 533
(2)
kSPS
Table 37-19. External Voltage Reference Input
Parameter Conditions Min Typ Max Units
ADVREF Input Voltage Range 2.6 V
DDIN
V
ADVREF Input Voltage Range 8-bit resolution mode 2.5 V
DDIN
V
ADVREF Average Current On 13 samples with ADC Clock = 5 MHz 200 250 µA
Current Consumption on VDDIN 0.55 1 mA
Table 37-20. Analog Inputs
Parameter Min Typ Max Units
Input Voltage Range 0V
ADVREF
Input Leakage Current 1µA
Input Capacitance 12 14 pF
Table 37-21. Transfer Characteristics
Parameter Conditions Min Typ Max Units
Resolution 10 Bit
Integral Non-linearity ±2 LSB
Differential Non-linearity No missing code ±1 LSB