Datasheet

325
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
nal address (IADR), the STOP bit must be set after the next-to-last data received. See Figure 30-10. For Internal
Address usage see Section 30.7.6.
Figure 30-9. Master Read with One Data Byte
Figure 30-10. Master Read with Multiple Data Bytes
30.7.6 Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave
address devices.
30.7.6.1 7-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or
write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
When performing read operations with an internal address, the TWI performs a write operation to set the internal
address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after
sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 30-12. See
Figure 30-11 and Figure 30-13 for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode register (TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0.
In the figures below the following abbreviations are used:
AS DADR R DATA N P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
TWD
N
AS DADR R DATA n A ADATA (n+1) A DATA (n+m)DATA (n+m)-1 PTWD
TXCOMP
Write START Bit
RXRDY
Write STOP Bit
after next-to-last data read
Read RHR
DATA n
Read RHR
DATA (n+1)
Read RHR
DATA (n+m)-1
Read RHR
DATA (n+m)
•S
Start
•Sr
Repeated Start
•P
Stop
•W
Write
•R
Read
•A
Acknowledge