AT91SAM ARM-based Flash MCU SAM7S512 SAM7S256 SAM7S128 SAM7S64 SAM7S321 SAM7S32 SAM7S161 SAM7S16 Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash – 512 Kbytes (SAM7S512) Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (SAM7S256) Organized
• Debug Unit (DBGU) • • • • • • • • • • • • • • • • • – 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention – Mode for General Purpose 2-wire UART Serial Communication Periodic Interval Timer (PIT) – 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) – 12-bit key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter May Be Stopped While the Processor is in Debug State or in Idle M
• Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions • Available in 64-lead LQFP Green or 64-pad QFN Green Package (SAM7S512/256/128/64/321/161) and 48-lead LQFP Green or 48-pad QFN Green Package (SAM7S32/16) 1. Description Atmel’s SAM7S is a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a high-speed Flash and an SRAM, a large set of peripherals, including a USB 2.
2. Block Diagram Figure 2-1. SAM7S512/256/128/64/321/161 Block Diagram TDI TDO TMS TCK ICE JTAG SCAN ARM7TDMI Processor JTAGSEL 1.
Figure 2-2. SAM7S32/16 Block Diagram TDI TDO TMS TCK ICE JTAG SCAN ARM7TDMI Processor JTAGSEL 1.
3. Signal Description Table 3-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDIN Voltage and ADC Regulator Power Supply Input Power 3.0 to 3.6V VDDOUT Voltage Regulator Output Power 1.85V nominal VDDFLASH Flash Power Supply Power 3.0V to 3.6V VDDIO I/O Lines Power Supply Power 3.0V to 3.6V or 1.65V to 1.95V VDDCORE Core Power Supply Power 1.65V to 1.95V VDDPLL PLL Power 1.65V to 1.
Table 3-1.
Table 3-1.
4. Package and Pinout The SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package. The SAM7S161 is available in a 64-Lead LQFP package. The SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package. 4.1 64-lead LQFP and 64-pad QFN Package Outlines Figure 4-1 and Figure 4-2 show the orientation of the 64-lead LQFP and the 64-pad QFN package. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-1.
4.2 64-lead LQFP and 64-pad QFN Pinout Table 4-1.
4.3 48-lead LQFP and 48-pad QFN Package Outlines Figure 4-3 and Figure 4-4 show the orientation of the 48-lead LQFP and the 48-pad QFN package. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-3. 48-lead LQFP Package (Top View) 36 25 37 24 48 13 1 12 Figure 4-4. 48-pad QFN Package (Top View) 36 25 37 24 48 13 1 4.4 12 48-lead LQFP and 48-pad QFN Pinout Table 4-2.
5. Power Considerations 5.1 Power Supplies The SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: z VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal. z VDDOUT pin. It is the output of the 1.8V voltage regulator. z VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.
Figure 5-1. 3.3V System Single Power Supply Schematic VDDFLASH Power Source ranges from 4.5V (USB) to 18V DC/DC Converter VDDIO VDDIN Voltage Regulator 3.
6. I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. 6.
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7. Processor and Architecture 7.1 ARM7TDMI Processor z RISC processor based on ARMv4T Von Neumann architecture z z z 7.2 Two instruction sets z ARM® high-performance 32-bit instruction set z Thumb® high code density 16-bit instruction set Three-stage pipeline architecture z Instruction Fetch (F) z Instruction Decode (D) z Execute (E) Debug and Test Features z z z 7.3 Runs at up to 55 MHz, providing 0.
7.
8. Memories 8.
z z Fast access time, 30 MHz single-cycle access in Worst Case conditions z Page programming time: 6 ms, including page auto-erase z Page programming without auto-erase: 3 ms z Full chip erase time: 15 ms z 10,000 write cycles, 10-year data retention capability z 16 lock bits, protecting 16 sectors of 32 pages z Protection Mode to secure contents of the Flash 16 Kbytes of Fast SRAM z 8.
Figure 8-1. SAM7S512/256/128/64/321/32/161/16 Memory Mapping Internal Memory Mapping Note: (1) Can be Flash or SRAM depending on REMAP.
8.7 Memory Mapping 8.7.1 Internal SRAM z The SAM7S512 embeds a high-speed 64-Kbyte SRAM bank. z The SAM7S256 embeds a high-speed 64-Kbyte SRAM bank. z The SAM7S128 embeds a high-speed 32-Kbyte SRAM bank. z The SAM7S64 embeds a high-speed 16-Kbyte SRAM bank. z The SAM7S321 embeds a high-speed 8-Kbyte SRAM bank. z The SAM7S32 embeds a high-speed 8-Kbyte SRAM bank. z The SAM7S161 embeds a high-speed 4-Kbyte SRAM bank.
8.8 Embedded Flash 8.8.1 Flash Overview z The Flash of the SAM7S512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. z The Flash of the SAM7S256 is organized in 1024 pages (single plane) of 256 bytes. The 262,144 bytes are organized in 32-bit words. z The Flash of the SAM7S128 is organized in 512 pages (single plane) of 256 bytes. The 131,072 bytes are organized in 32-bit words.
8.8.3 Lock Regions 8.8.3.1 SAM7S512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.
The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.8.3.6 SAM7S161/16 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S161/16 contains 8 lock regions and each lock region contains 32 pages of 64 bytes.
8.8.6 Calibration Bits Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. 8.9 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.
Figure 9-1. System Controller Block Diagram (SAM7S512/256/128/64/321/161) jtag_nreset System Controller Boundary Scan TAP Controller nirq irq0-irq1 Advanced Interrupt Controller fiq periph_irq[2..
Figure 9-2. System Controller Block Diagram (SAM7S32/16) jtag_nreset System Controller Boundary Scan TAP Controller nirq irq0 Advanced Interrupt Controller fiq periph_irq[2..
9.1 Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. In addition, it controls the internal resets and the NRST pin open-drain output. It allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement.
9.2 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: z RC Oscillator ranges between 22 kHz and 42 kHz z Main Oscillator frequency ranges between 3 and 20 MHz z Main Oscillator can be bypassed z PLL output ranges between 80 and 220 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-3.
Figure 9-4. Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK PCK int Idle Mode Prescaler /1,/2,/4,...,/64 MCK Peripherals Clock Controller periph_clk[2..14] ON/OFF Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 USB Clock Controller ON/OFF PLLCK 9.4 Divider /1,/2,/4 pck[0..
9.5 Debug Unit z z z Comprises: z One two-pin UART z One Interface for the Debug Communication Channel (DCC) support z One set of Chip ID Registers z One Interface providing ICE Access Prevention Two-pin UART z Implemented features are compatible with the USART z Programmable Baud Rate Generator z Parity, Framing and Overrun Error z Automatic Echo, Local Loopback and Remote Loopback Channel Modes Debug Communication Channel Support z z Note: 9.
9.8 9.9 Real-time Timer z 32-bit free-running counter with alarm running on prescaled SCLK z Programmable 16-bit prescaler for SLCK accuracy compensation PIO Controller z One PIO Controller, controlling 32 I/O lines (21 for SAM7S32/16) z Fully programmable through set/clear registers z Multiplexing of two peripheral functions per I/O line z For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) z 9.
10. Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in Figure 8-1 on page 20. 10.2 Peripheral Identifiers The SAM7S Series embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the SAM7S512/256/128/64/321/161. Table 10-2 defines the Peripheral Identifiers of the SAM7S32/16.
Table 10-2. Peripheral Identifiers (SAM7S32/16) 10.
10.4 PIO Controller A Multiplexing Table 10-3.
Table 10-4.
10.5 Serial Peripheral Interface 10.6 10.
10.8 10.
Programmable center or left aligned output waveform 10.11 USB Device Port (Does not pertain to SAM7S32/16) USB V2.0 full-speed compliant, 12 Mbits per second. Embedded USB V2.0 full-speed transceiver Embedded 328-byte dual-port RAM for endpoints Four endpoints Endpoint 0: 8 bytes Endpoint 1 and 2: 64 bytes ping-pong Endpoint 3: 64 bytes Ping-pong Mode (two memory banks) for isochronous and bulk endpoints Suspend/resume logic 10.
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11. ARM7TDMI Processor Overview 11.1 Overview The ARM7TDMI core executes both the 32-bit ARM® and 16-bit Thumb® instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages.
11.2 ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) 11.2.1 Instruction Type Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). 11.2.2 Data Type ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to fourbyte boundaries and half words to two-byte boundaries.
Table 11-1.
• two interrupt disable bits (one for each type of interrupt) • one bit to indicate ARM or Thumb execution • five bits to encode the current processor mode All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception. 11.2.4.3 Exception Types The ARM7TDMI supports five types of exception and a privileged processing mode for each type.
Table 11-2. 11.2.
Table 11-3.
12. Debug and Test Features 12.1 Description The SAM7S Series Microcontrollers feature a number of complementary debug and test capabilities. A common JTAG/ICE (EmbeddedICE) port is used for standard debugging functions, such as downloading code and singlestepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM.
12.3 Application Examples 12.3.1 Debug Environment Figure 12-2 on page 48 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2.
12.3.2 Test Environment Figure 12-3 on page 49 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 12-3.
12.4 Debug and Test Pin Description Table 12-1.
12.5 Functional Description 12.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 12.5.2 EmbeddedICE™ (Embedded In-circuit Emulator) The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is examined through an ICE/JTAG port.
Table 12-2. SAM7S Series Debug Unit Chip ID (Continued) AT91SAM7S128 Rev B 0x270A0741 AT91SAM7S128 Rev C 0x270A0742 AT91SAM7S128 Rev D 0x270A0743 AT91SAM7S256 Rev A 0x270D0940 AT91SAM7S256 Rev B 0x270B0941 AT91SAM7S256 Rev C 0x270B0942 AT91SAM7S256 Rev D 0x270B0943 AT91SAM7S512 Rev A 0x270B0A40 AT91SAM7S512 Rev B 0x270B0A4F For further details on the Debug Unit, see the Debug Unit section. 12.5.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.
Table 12-3.
Table 12-3.
Table 12-3. SAM7Sxx JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type 15 14 INPUT PA1/PGMEN1 IN/OUT OUTPUT 13 CONTROL 12 INPUT 11 PA0/PGMEN0 IN/OUT OUTPUT 10 CONTROL 9 INPUT(1) 8 PA29 IN/OUT OUTPUT(1) 7 CONTROL(1) 6 INPUT(1) 5 PA30 IN/OUT OUTPUT(1) 4 CONTROL(1) 3 INPUT(1) 2 PA31 IN/OUT 0 OUTPUT(1) CONTROL(1) 1 Note: Associated BSR Cells ERASE IN INPUT 1. Does not pertain to SAM7S32.
12.5.5 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 The JTAG D is used in the IEEE 1149.1 JTAG Boundary Scan. • VERSION[31:28]: Product Version Number Set to 0x0.
13. Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. A brownout detection is also available to prevent the processor from falling into an unpredictable state. 13.2 Block Diagram Figure 13-1.
13.3 Functional Description 13.3.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin.
13.3.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
13.3.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 13.3.4.1 Power-up Reset When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock.
13.3.4.2 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup.
13.3.4.3 Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left Y Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered.
13.3.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal.
13.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Power-up Reset • Brownout Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed below: • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated.
Figure 13-9.
13.4 Reset Controller (RSTC) User Interface Table 13-1.
13.4.1 Reset Controller Control Register Register Name: RSTC_CR Access Type: 31 Write-only 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect.
13.4.2 Reset Controller Status Register Register Name: RSTC_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 BODSTS 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
13.4.3 Reset Controller Mode Register Register Name: RSTC_MR Access Type: 31 Read/Write 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 BODIEN 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 – 5 – 4 URSTIEN 3 – 1 – 0 URSTEN ERSTL 2 – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.
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14. Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value. 14.2 Block Diagram Figure 14-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK RTTINCIEN reload 16-bit Divider set 0 RTT_MR RTTRST RTT_SR 1 RTTINC reset 0 rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR reset CRTV RTT_SR ALMS set rtt_alarm = RTT_AR 14.
The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented.
14.4 Real-time Timer (RTT) User Interface Table 14-1.
14.4.1 Real-time Timer Mode Register Register Name: RTT_MR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer.
14.4.2 Real-time Timer Alarm Register Register Name: RTT_AR Access Type: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer.
14.4.3 Real-time Timer Value Register Register Name: RTT_VR Access Type: 31 Read-only 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
14.4.4 Real-time Timer Status Register Register Name: RTT_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.
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15. Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1.
15.3 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
15.4 Periodic Interval Timer (PIT) User Interface Table 15-1.
15.4.1 Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 PITIEN 24 PITEN 23 – 22 – 21 – 20 – 19 18 17 16 15 14 13 12 11 10 9 8 3 2 1 0 PIV PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
15.4.2 Periodic Interval Timer Status Register Register Name: PIT_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
15.4.3 Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: 31 Read-only 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
15.4.4 Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type: 31 Read-only 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
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16. Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.2 Block Diagram Figure 16-1.
16.3 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
Figure 16-2.
16.4 Watchdog Timer (WDT) User Interface Table 16-1. Offset Register Mapping Register Name Access Reset 0x00 Control Register WDT_CR Write-only - 0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000 16.4.
16.4.2 Watchdog Timer Mode Register Register Name: WDT_MR Access Type: Read-write Once 31 – 30 – 29 WDIDLEHLT 28 WDDBGHLT 27 23 22 21 20 19 11 26 25 24 18 17 16 10 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
16.4.3 Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
17. Voltage Regulator Mode Controller (VREG) 17.1 Overview The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake up the Voltage Regulator in Normal Mode.
17.2 Voltage Regulator Power Controller (VREG) User Interface Table 17-1. Register Mapping Offset Register Name 0x60 Voltage Regulator Mode Register VREG_MR Access Reset Read-write 0x0 17.2.
18. Memory Controller (MC) 18.1 Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a simple bus arbiter, an address decoder, an abort status, a misalignment detector and an Embedded Flash Controller. 18.2 Block Diagram Figure 18-1.
It is made up of: • A bus arbiter • An address decoder • An abort status • A misalignment detector • An Embedded Flash Controller The MC handles only little-endian mode accesses. The masters work in little-endian mode only. 18.3.1 Bus Arbiter The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the two masters. The Peripheral DMA Controller has the highest priority; the ARM processor has the lowest one. 18.3.
If an access is done in the address area 0x0030 000 to 0x003F FFFF, no abort is generated. Figure 18-3. Internal Memory Mapping 0x0000 0000 Internal Memory Area 0 1M Bytes Internal Memory Area 1 Internal Flash 1M Bytes Internal Memory Area 2 Internal SRAM 1M Bytes 0x000F FFFF 0x0010 0000 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 Undefined Areas (Abort) 253M bytes 0x0FFF FFFF 18.3.2.
To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status register set. The full 32-bit wide abort address is saved in MC_AASR.
Table 18-1. Register Mapping Offset Register Name Access Reset 0x0C-0x5C Reserved – – – 0x60 EFC0 Configuration Registers 0x70 EFC1 Configuration Registers (1) Note: 1. See Section 19. “Embedded Flash Controller (EFC)” on page 105. SAM7S512 only.
18.4.1 MC Remap Control Register Register Name: MC_RCR Access Type: Write-only Offset: 0x00 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – RCB • RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices.
18.4.2 MC Abort Status Register Register Name: MC_ASR Access Type: Read-only Reset Value: 0x0 Offset: 0x04 31 30 29 28 27 26 25 24 – – – – – – SVMST1 SVMST0 23 22 21 20 19 18 17 16 – – – – – – MST1 MST0 15 14 13 12 11 10 9 – – – – 7 6 5 4 3 2 1 0 – – – – – – MISADD UNDADD ABTTYP 8 ABTSZ • UNDADD: Undefined Address Abort Status 0: The last abort was not due to the access of an undefined address in the address space.
0: The last aborted access was not due to the ARM7TDMI. 1: The last aborted access was due to the ARM7TDMI. • SVMST0: Saved PDC Abort Source 0: No abort due to the PDC occurred. 1: At least one abort due to the PDC occurred. • SVMST1: Saved ARM7TDMI Abort Source 0: No abort due to the ARM7TDMI occurred. 1: At least one abort due to the ARM7TDMI occurred. 18.4.
19. Embedded Flash Controller (EFC) 19.1 Overview The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the interface of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands. The SAM7S512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the Security bit and GPNVM bit.
Figure 19-1.
19.2.2 Read Operations An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added in order to start access at following address during the second read, thus increasing performance when the processor is running in Thumb mode (16-bit instruction set). See Figure 19-2, Figure 19-3 and Figure 19-4. This optimization concerns only Code Fetch and not Data. The read operations can be performed with or without wait state.
Figure 19-4.
19.2.3 Write Operations The internal memory area reserved for the embedded Flash can also be written through a write-only latch buffer. Write operations take into account only the 8 lowest address bits and thus wrap around within the internal memory area address space and appear to be repeated 1024 times within it. Write operations can be prevented by programming the Memory Protection Unit of the product. Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Figure 19-5.
Figure 19-6. Example of Partial Page Programming 32 bits wide 32 bits wide 16 words 16 words FF FF FF FF FF FF FF FF FF FF 16 words FF FF FF FF FF 16 words FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... FF FF FF FF FF CA FE FF FF CA CA FE FE FF FF ... FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... FF FF FF FF FF FF FF FF FF FF FF FF FF ... Step 1. Erase All Flash Page 7 erased ... ... ... ...
When programming is complete, the bit FRDY bit in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Two errors can be detected in the MC_FSR register after a programming sequence: • Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register. • Lock Error: At least one lock region to be erased is protected.
• When the bit is set, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.
19.3 Embedded Flash Controller (EFC) User Interface The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. The SAM7S512 is equipped with two EFCs, EFC0 and EFC1, as described in the Register Mapping tables and Register descriptions that follow. Table 19-3.
19.3.1 MC Flash Mode Register Register Name: MC_FMR Access Type: Read-write Offset: (EFC0) 0x60 Offset: (EFC1) 0x70 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 FMCN 15 – 14 – 13 – 12 – 11 – 10 – 9 7 NEBP 6 – 5 – 4 – 3 PROGE 2 LOCKE 1 – 8 FWS 0 FRDY • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready generates an interrupt. • LOCKE: Lock Error Interrupt Enable 0: Lock Error does not generate an interrupt.
Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the number of Master Clock cycles in one microsecond. When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up. Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds.
19.3.2 MC Flash Command Register Register Name: MC_FCR Access Type: Write-only Offset: (EFC0) 0x64 Offset: (EFC1) 0x74 31 30 29 28 27 26 25 24 19 – 18 – 17 11 10 9 8 3 2 1 0 KEY 23 – 22 – 21 – 20 – 15 14 13 12 16 PAGEN PAGEN 7 – 6 – 5 – 4 – FCMD • FCMD: Flash Command This field defines the Flash commands: FCMD Operations 0000 No command. Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR.
• PAGEN: Page Number Command PAGEN Description Write Page Command PAGEN defines the page number to be written. Write Page and Lock Command PAGEN defines the page number to be written and its associated lock region. Erase All Command This field is meaningless Set/Clear Lock Bit Command PAGEN defines one page number of the lock region to be locked or unlocked. Set/Clear General Purpose NVM Bit Command PAGEN defines the general-purpose bit number.
19.3.
MC_FSR, LOCKSx Product Specific Map SAM7S512 SAM7S256 SAM7S128 SAM7S64 SAM7S321 SAM7S32 SAM7S161 SAM7S16 Denomination 32() 16 8 16 8 8 8 8 Number of Lock Bits LOCKS0 LOCKS0 LOCKS0 LOCKS0 LOCKS0 LOCKS0 LOCKS0 LOCKS0 Lock Region 0 Lock Status LOCKS1 LOCKS1 LOCKS1 LOCKS1 LOCKS1 LOCKS1 LOCKS1 LOCKS1 Lock Region 1 Lock Status LOCKS2 LOCKS2 LOCKS2 LOCKS2 LOCKS2 LOCKS2 LOCKS2 LOCKS2 Lock Region 2 Lock Status LOCKS3 LOCKS3 LOCKS3 LOCKS3 LOCKS3 LOCKS3 LOCKS3 LOCKS3
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SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 122
20. Fast Flash Programming Interface (FFPI) 20.1 Overview The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. The serial interface uses the standard IEEE 1149.1 JTAG protocol.
20.2 Parallel Fast Flash Programming 20.2.1 Device Configuration In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected. Figure 20-1. SAM7S512/256/128/64/321/161 Parallel Programming Interface VDDIO VDDIO VDDIO GND TST PGMEN0 PGMEN1 PGMEN2 NCMD RDY PGMNCMD PGMRDY NOE PGMNOE VDDFLASH PGMNVALID GND NVALID MODE[3:0] PGMM[3:0] DATA[15:0] PGMD[15:0] 0 - 50MHz XIN VDDCORE VDDIO VDDPLL Figure 20-2.
Table 20-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDFLASH Flash Power Supply Power VDDIO I/O Lines Power Supply Power VDDCORE Core Power Supply Power VDDPLL PLL Power Supply Power GND Ground Ground Clocks Main Clock Input. This input can be tied to GND. In this case, the device is clocked by the internal RC oscillator.
20.2.2 Signal Names Depending on the MODE settings, DATA is latched in different internal registers. Table 20-2. Mode Coding MODE[3:0] Symbol Data 0000 CMDE Command Register 0001 ADDR0 Address Register LSBs 0010 ADDR1 0011 ADDR2 0100 ADDR3 Address Register MSBs 0101 DATA Data Register Default IDLE No register When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] or DATA[7:0] signals) is stored in the command register. Note: DATA[7:0] pertains to the SAM7S32/16.
20.2.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: • Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL. • Apply XIN clock within TPOR_RESET if an external clock is available. • Wait for TPOR_RESET • Start a read or write handshaking. Note: 20.2.4 After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock (> 32 kHz) is connected to XIN, then the device switches on the external clock.
Table 20-4. Write Handshake Step Programmer Action Device Action Data I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latches MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Releases MODE and DATA signals Executes command and polls NCMD high Input 5 Sets NCMD signal Executes command and polls NCMD high Input 6 Waits for RDY high Sets RDY Input 20.2.4.
Table 20-5. Read Handshake Step Programmer Action Device Action DATA I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latch MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Sets DATA signal in tristate Waits for NOE Low Input 5 Clears NOE signal 6 Waits for NVALID low 7 Tristate Sets DATA bus in output mode and outputs the flash contents.
20.2.5 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page 126. Each command is driven by the programmer through the parallel interface running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash.
Table 20-7. Read Command (Continued) Step Handshake Sequence MODE[3:0] DATA[7:0] n+2 Write handshaking ADDR2 Memory Address n+3 Write handshaking ADDR3 Memory Address n+4 Read handshaking DATA *Memory Address++ n+5 Read handshaking DATA *Memory Address++ ... ... ... ... 20.2.5.2 Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages.
Table 20-9. Write Command (Continued) Step Handshake Sequence MODE[3:0] DATA[7:0] ... ... ... ... n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking ADDR2 Memory Address n+3 Write handshaking ADDR3 Memory Address n+4 Write handshaking DATA *Memory Address++ n+5 Write handshaking DATA *Memory Address++ ... ... ... ... The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command.
Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set.. Table 20-12. Get Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0] 1 Write handshaking CMDE GLB 2 Read handshaking DATA Lock Bit Mask Status 0 = Lock bit is cleared 1 = Lock bit is set 20.2.5.5 Flash General-purpose NVM Commands General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB).
• Power-off the chip • Power-on the chip with TST = 0 • Assert Erase during a period of more than 220 ms • Power-off the chip Then it is possible o return to FFPI mode and check that Flash is erased. 20.2.5.7 SAM7S512 Select EFC Command The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default EFC controller is EFC0. The Select EFC command (SEFC) allows selection of the current EFC controller. Table 20-16.
Table 20-18. Write Command (Continued) Step Handshake Sequence MODE[3:0] DATA[7:0] 6 Write handshaking DATA *Memory Address++ 7 Write handshaking DATA *Memory Address++ ... ... ... ... n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking ADDR2 Memory Address n+3 Write handshaking ADDR3 Memory Address n+4 Write handshaking DATA *Memory Address++ n+5 Write handshaking DATA *Memory Address++ ... ... ... ... 20.
20.3 Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a description of the TAP controller states. In this mode, data read/written from/to the embedded Flash of the device are transmitted through the JTAG interface of the device. 20.3.
Table 20-20. Signal Description List (Continued) Signal Name Function Type Active Level Comments Test TST Test Mode Select Input High Must be connected to VDDIO.
Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A register is read by scanning its address into the address field and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data.
20.3.4.1 Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at any valid address in the memory plane. This address must be word-aligned. The address is automatically incremented. Table 20-22. Read Command Read/Write DR Data Write (Number of Words to Read) << 16 | READ Write Address Read Memory [address] Read Memory [address+4] ... ...
All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB command. Table 20-24. Full Erase Command Read/Write DR Data Write EA 20.3.4.4 Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated at the same time. Bit 0 of Bit Mask corresponds to the first lock bit and so on.
20.3.4.6 Flash Security Bit Command Security bits can be set using Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. Only an event on the Erase pin can erase the security bit once the contents of the Flash have been erased. The SAM7S512 security bit is controlled by the EFC0. To use the Set Security Bit command, the EFC0 must be selected using the Select EFC command. Table 20-29.
20.3.4.8 Memory Write Command This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. An internal address buffer is automatically increased. Table 20-31. Write Command Read/Write DR Data Write (Number of Words to Write) << 16 | (WRAM) Write Address Write Memory [address] Write Memory [address+4] Write Memory [address+8] Write Memory [address+(Number of Words to Write - 1)* 4] 20.3.4.
21. SAM7 Boot Program 21.1 Description The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. SAM-BA® Boot is then executed. It waits for transactions either on the USB device or on the DBGU serial port. 21.2 Flow Diagram The Boot Program implements the algorithm shown in Figure 21-1 or Figure 21-2. Figure 21-1.
21.3 Device Initialization with USB Initialization follows the steps described below: 1. FIQ initialization 1. Stack setup for ARM supervisor mode 2. Setup the Embedded Flash Controller 3. External Clock detection 4. Main oscillator frequency detection if no external clock detected 5. Switch Master Clock on Main Oscillator 6. Copy code into SRAM 7. C variable initialization 8. PLL setup: PLL is initialized to generate a 48 MHz clock necessary to use the USB Device 9.
21.5 SAM-BA Boot The SAM-BA boot principle is to: – Check if USB Device enumeration has occurred – Check if the Auto Baudrate sequence has succeeded (see Figure 21-3) Figure 21-3.
– Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as shown in Table 21-1. Table 21-1.
21.5.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work.
The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows®, from Windows98SE to WindowsXP. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver.
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21.6 Hardware and Software Constraints • SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available sizes for the user codes are as follows: 57344 bytes for SAM7S512, 57344 bytes for SAM7S256, 24576 bytes for SAM7S128, 8192 bytes for SAM7S64, 2048 bytes for SAM7S321 and SAM7S32, 3840 bytes for SAM7S161 and SAM7S16. • USB requirements: (Does not pertain to SAM7S32/16) – 18.432 MHz Quartz – PIOA16 dedicated to the USB Pull-up Table 21-4.
22. Peripheral DMA Controller (PDC) 22.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor intervention and removes the processor interrupt-handling overhead.
22.3 Functional Description 22.3.1 Configuration The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to. Per peripheral, it contains four 32-bit Pointer Registers (RPR, RNPR, TPR, and TNPR) and four 16-bit Counter Registers (RCR, RNCR, TCR, and TNCR).
Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to re-enable the triggers. For each channel, two status bits indicate the end of the current buffer (ENDRX, ENDTX) and the end of both current and next buffer (RXBUFF, TXBUFE).
22.4.1 PDC Receive Pointer Register Register Name: PERIPH_RPR Access Type: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Address Address of the next receive transfer. 22.4.
22.4.3 PDC Transmit Pointer Register Register Name: PERIPH_TPR Access Type: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Pointer Address Address of the transmit buffer. 22.4.
22.4.5 PDC Receive Next Pointer Register Register Name: PERIPH_RNPR Access Type: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when the current buffer is full. 22.4.
22.4.7 PDC Transmit Next Pointer Register Register Name: PERIPH_TNPR Access Type: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer is empty. 22.4.
22.4.9 PDC Transfer Control Register Register Name: PERIPH_PTCR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXTDIS TXTEN 7 6 5 4 3 2 1 0 – – – – – – RXTDIS RXTEN • RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables the receiver PDC transfer requests if RXTDIS is not set. • RXTDIS: Receiver Transfer Disable 0 = No effect.
22.4.10 PDC Transfer Status Register Register Name: PERIPH_PTSR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – TXTEN 7 6 5 4 3 2 1 0 – – – – – – – RXTEN • RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. 1 = Receiver PDC transfer requests are enabled.
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23. Advanced Interrupt Controller (AIC) 23.1 Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and realtime overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
23.3 Application Block Diagram Figure 23-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 23.4 AIC Detailed Block Diagram Figure 23-3.
23.6 Product Dependencies 23.6.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path. 23.6.2 Power Management The Advanced Interrupt Controller is continuously clocked.
23.7 23.7.1 Functional Description Interrupt Source Control 23.7.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode.
23.7.1.5 Internal Interrupt Source Input Stage Figure 23-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Edge AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR 23.7.1.6 External Interrupt Source Input Stage Figure 23-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos.
23.7.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. • Occurrence, either at the processor level or at the AIC level. • The execution time of the instruction in progress when the interrupt occurs. • The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations.
23.7.2.3 Internal Interrupt Edge Triggered Source Figure 23-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active 23.7.2.4 Internal Interrupt Level Sensitive Source Figure 23-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 23.7.3 Normal Interrupt 23.7.3.
23.7.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted.
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR.
23.7.4 Fast Interrupt 23.7.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. 23.7.4.2 Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller.
ters, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example).
Figure 23-10. Fast Forcing Source 0 _ FIQ AIC_IPR Input Stage Automatic Clear AIC_IMR nFIQ Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR Source n AIC_IPR Input Stage Priority Manager Automatic Clear AIC_IMR nIRQ Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n.
23.7.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR.
enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. 23.7.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode.
23.8 Advanced Interrupt Controller (AIC) User Interface 23.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only an ± 4-Kbyte offset. Table 23-2.
Access Type: Read/Write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – SRCTYPE PRIOR • PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the related SMR register AIC_SMRx.
23.8.3 AIC Source Vector Register Register Name: AIC_SVR0..AIC_SVR31 Access Type: Read/Write Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. 23.8.
23.8.5 AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Read-only Reset Value: 0 x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. 23.8.
23.8.
23.8.9 AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read-only Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NIFQ • NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active. 23.8.
23.8.11 AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect.
23.8.13 AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt.
23.8.15 AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type: Read/Write Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. 23.8.
23.8.17 AIC Fast Forcing Enable Register Register Name: AIC_FFER Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Enable 0 = No effect.
23.8.
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 186
24. Clock Generator 24.1 Overview The Clock Generator is made up of 1 PLL, a Main Oscillator, as well as an RC Oscillator. It provides the following clocks: • SLCK, the Slow Clock, which is the only permanent clock within the system • MAINCK is the output of the Main Oscillator • PLLCK is the output of the Divider and PLL block The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 25.9. However, the Clock Generator registers are named CKGR_.
Figure 24-2. Typical Crystal Connection SAM7S Microcontroller XIN XOUT GND 1K 24.3.2 Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the frequency rises. 24.3.3 Main Oscillator Control To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected.
24.3.5 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly. 24.
frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_PLLR are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0.
25. Power Management Controller (PMC) 25.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks: • MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device.
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 25.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register). Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers.
The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s) (Does not pertain to SAM7S32/16.) Code Example: write_register(CKGR_PLLR,0x00040805) If PLL and divider are enabled, the PLL input clock is the main clock. PLL output clock is PLL input clock multiplied by 5. Once CKGR_PLLR has been written, LOCK bit will be set after eight slow clock cycles. 4.
wait (MCKRDY=1) The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 5. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 3 Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled.
write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled.
25.8 Clock Switching Details 25.8.1 Master Clock Switching Timings Table 25-1 gives the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 25-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock – 4 x SLCK + 2.
Figure 25-4. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR Figure 25-5.
Figure 25-6.
25.9 Power Management Controller (PMC) User Interface Table 25-2.
25.9.1 PMC System Clock Enable Register Register Name: PMC_SCER Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP – – – – – – PCK • PCK: Processor Clock Enable 0 = No effect. 1 = Enables the Processor clock. • UDP: USB Device Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock of the USB Device Port.
25.9.2 PMC System Clock Disable Register Register Name: PMC_SCDR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP – – – – – – PCK • PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode. • UDP: USB Device Port Clock Disable 0 = No effect.
25.9.3 PMC System Clock Status Register Register Name: PMC_SCSR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP – – – – – – PCK • PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled.
25.9.4 PMC Peripheral Clock Enable Register Register Name: PMC_PCER Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0 = No effect.
25.9.6 PMC Peripheral Clock Status Register Register Name: PMC_PCSR Access Type: Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 – – • PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled.
25.9.7 PMC Clock Generator Main Oscillator Register Register Name: CKGR_MOR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 OSCBYPASS 0 MOSCEN OSCOUNT 7 – 6 – 5 – 4 – • MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Oscillator is disabled. 1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0.
25.9.8 PMC Clock Generator Main Clock Frequency Register Register Name: CKGR_MCFR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled.
25.9.9 PMC Clock Generator PLL Register Register Name: CKGR_PLLR Access Type: Read-write 31 – 30 – 29 23 22 21 28 USBDIV 20 27 – 26 25 MUL 24 19 18 17 16 11 10 9 8 2 1 0 MUL 15 14 13 12 OUT 7 PLLCOUNT 6 5 4 3 DIV Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. • DIV: Divider DIV Divider Selected 0 Divider output is 0 1 Divider is bypassed 2 - 255 Divider output is the selected clock divided by DIV.
25.9.10 PMC Master Clock Register Register Name: PMC_MCKR Access Type: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – PRES CSS • CSS: Master Clock Selection CSS Clock Source Selection 0 0 Slow Clock is selected 0 1 Main Clock is selected 1 0 Reserved 1 1 PLL Clock is selected.
25.9.
25.9.
25.9.
25.9.14 PMC Status Register Register Name: PMC_SR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 – – – – MCKRDY LOCK – MOSCS • MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized. • LOCK: PLL Lock Status 0 = PLL is not locked 1 = PLL is locked.
25.9.
26. Debug Unit (DBGU) 26.1 Overview The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. Moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum.
26.2 Block Diagram Figure 26-1. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB Debug Unit DTXD Transmit Power Management Controller Parallel Input/ Output Baud Rate Generator MCK Receive DRXD COMMRX DCC Handler R ARM Processor COMMTX Chip ID nTRST ICE Access Handler Interrupt Control dbgu_irq Power-on Reset force_ntrst Table 26-1.
26.3 Product Dependencies 26.3.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. 26.3.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock.
26.4.2 Receiver 26.4.2.1 Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped.
Figure 26-5. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 S P D0 D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 26.4.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 26-6.
Figure 26-8. Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 26.4.3 RSTSTA Transmitter 26.4.3.1 Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1.
Figure 26-10. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register DTXD Data 0 S Data 0 Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR 26.4.4 Write Data 1 in DBGU_THR Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel.
Figure 26-11. Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter 26.4.6 TXD VDD Disabled Disabled RXD TXD Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
• EXT - shows the use of the extension identifier register • NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size • ARCH - identifies the set of embedded peripheral • SRAMSIZ - indicates the size of the embedded SRAM • EPROC - indicates the embedded ARM processor • VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 26.4.
26.5 Debug Unit (DBGU) User Interface Table 26-2.
26.5.1 Name: Debug Unit Control Register DBGU_CR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. • RSTTX: Reset Transmitter 0 = No effect.
26.5.
26.5.
26.5.
26.5.
26.5.6 Name: Debug Unit Status Register DBGU_SR Access Type: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active.
26.5.7 Name: Debug Unit Receiver Holding Register DBGU_RHR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
26.5.8 Name: Debug Unit Transmit Holding Register DBGU_THR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
26.5.
26.5.
• NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 Size 0 0 0 0 None 0 0 0 1 8K bytes 0 0 1 0 16K bytes 0 0 1 1 32K bytes 0 1 0 0 Reserved 0 1 0 1 64K bytes 0 1 1 0 Reserved 0 1 1 1 128K bytes 1 0 0 0 Reserved 1 0 0 1 256K bytes 1 0 1 0 512K bytes 1 0 1 1 Reserved 1 1 0 0 1024K bytes 1 1 0 1 Reserved 1 1 1 0 2048K bytes 1 1 1 1 Reserved • SRAMSIZ: Internal SRAM Size SRAMSIZ Size 0 0 0 0 Reserved 0 0 0 1 1K byt
• ARCH: Architecture Identifier ARCH Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x37 0011 0111 CAP7 Series 0x39 0011 1001 CAP9 Series 0x3B 0011 1011 CAP11 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0110 0000 AT91SAM7Axx Series 0x61 0110 0001 AT91SAM7AQxx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 011
26.5.11 Name: Debug Unit Chip ID Extension Register DBGU_EXID Access Type: 31 Read-only 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. 26.5.
27. Parallel Input/Output Controller (PIO) 27.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
27.2 Block Diagram Figure 27-1. Block Diagram PIO Controller AIC PMC PIO Interrupt PIO Clock Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 27-2.
27.3 Product Dependencies 27.3.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
27.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 27-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 27-3.
27.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pullup Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines.
Figure 27-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 27.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.
Figure 27-5. Input Glitch Filter Timing MCK up to 1.5 cycles Pin Level 1 cycle 1 cycle 1 cycle 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles up to 2.5 cycles PIO_PDSR if PIO_IFSR = 1 27.4.10 1 cycle up to 2 cycles Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line.
• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor • Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts • Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter • I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor • I/O lines 20
27.6 Programmable Multibit ECC Error Location (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 27-2.
Table 27-2.
27.6.1 Name: PIO Controller PIO Enable Register PIO_PER Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 27.6.
27.6.3 Name: PIO Controller PIO Status Register PIO_PSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active).
27.6.5 Name: PIO Controller Output Disable Register PIO_ODR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line. 27.6.
27.6.7 Name: PIO Controller Input Filter Enable Register PIO_IFER Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. 27.6.
27.6.9 Name: PIO Controller Input Filter Status Register PIO_IFSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. 27.6.
27.6.11 Name: PIO Controller Clear Output Data Register PIO_CODR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 27.6.
27.6.13 Name: PIO Controller Pin Data Status Register PIO_PDSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. 27.6.
27.6.15 Name: PIO Controller Interrupt Disable Register PIO_IDR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. 27.6.
27.6.17 Name: PIO Controller Interrupt Status Register PIO_ISR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
27.6.19 Name: PIO Multi-driver Disable Register PIO_MDDR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line. 27.6.
27.6.21 Name: PIO Pull Up Disable Register PIO_PUDR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line. 27.6.
27.6.23 Name: PIO Pull Up Status Register PIO_PUSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. 27.6.
27.6.25 Name: PIO Peripheral B Select Register PIO_BSR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function. 27.6.
27.6.27 Name: PIO Output Write Enable Register PIO_OWER Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. 27.6.
27.6.29 Name: PIO Output Write Status Register PIO_OWSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line.
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28. Serial Peripheral Interface (SPI) 28.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
28.3 Application Block Diagram Figure 28-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 NC NPCS3 MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 28.4 Signal Description Table 28-1.
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28.6 Functional Description 28.6.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode.
Figure 28-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 28-4.
28.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
28.6.3.1 Master Mode Block Diagram Figure 28-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
28.6.3.2 Master Mode Flow Diagram Figure 28-6. Master Mode Flow Diagram S SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register.
Figure 28-8. Peripheral Deselection CSAAT = 0 TDRE NPCS[0..3] CSAAT = 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B A B DLYBCS PCS = B DLYBCS PCS = B Write SPI_TDR 28.6.3.8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal.
When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register.
28.7 Serial Peripheral Interface (SPI) User Interface User Interface Table 28-3.
28.7.1 Name: SPI Control Register SPI_CR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer.
28.7.2 Name: SPI Mode Register SPI_MR Access Type: 31 Read-write 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 LLB – – MODFDIS PCSDEC PS MSTR PCS • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.
This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
28.7.3 Name: SPI Receive Data Register SPI_RDR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer.
28.7.4 Name: SPI Transmit Data Register SPI_TDR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
28.7.
1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. • SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. Note: 1.
28.7.
28.7.
28.7.
28.7.9 Name: SPI Chip Select Register SPI_CSR0... SPI_CSR3 Access Type: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT – NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS • CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK).
BITS Bits Per Transfer 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCKSPCK Baudrate = ---------------SCBR Programming the SCBR field at 0 is forbidden.
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29. Two-wire Interface (TWI) SAM7S512/256/128/64/321/32 NOTE: This definition of the TWI does not pertain to SAM7S16/161. For SAM7S16/161, see Section 30. 29.1 Overview The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format.
29.3 Block Diagram Figure 29-1. Block Diagram APB Bridge TWCK PIO PMC MCK TWD Two-wire Interface TWI Interrupt 29.4 AIC Application Block Diagram Figure 29-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 29.4.1 I/O Lines Description Table 29-3. 29.5 29.5.
high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: • Program the PIO controller to: – Dedicate TWD and TWCK as peripheral lines. – Define TWD and TWCK as open-drain. 29.5.2 Power Management • Enable the peripheral clock.
• Master transmitter mode • Master receiver mode The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it generates the clock according to the value programmed in the Clock Waveform Generator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks. 29.6.
Figure 29-7. Master Write with One Byte Internal Address and Multiple Data Bytes TWD S DADR W A IADR(7:0) A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) 29.6.4 Write THR (Data n+1) Write THR (Data n+x) STOP sent automaticaly Last data sent (ACK received and TXRDY = 1) Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device.
Figure 29-9.
29.6.5 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 29.6.5.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
29.6.5.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2.
29.6.6 Read/Write Flowcharts The following flowcharts shown in Figure 29-13, Figure 29-14 on page 304, Figure 29-15 on page 305, Figure 29-16 on page 306, Figure 29-17 on page 307 and Figure 29-18 on page 308 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 29-13.
Figure 29-14.
Figure 29-15.
Figure 29-16.
Figure 29-17.
Figure 29-18.
29.7 Two-wire Interface (TWI) User Interface Table 29-4.
29.7.1 TWI Control Register Register Name: TWI_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
29.7.2 TWI Master Mode Register Register Name: TWI_MMR Address Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 DADR 18 17 16 15 – 14 – 13 – 12 MREAD 11 – 10 – 9 7 – 6 – 5 – 4 – 3 – 2 – 1 – 8 IADRSZ 0 – • IADRSZ: Internal Device Address Size Table 29-5.
29.7.3 TWI Internal Address Register Register Name: TWI_IADR Access Type: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. – Low significant byte address in 10-bit mode addresses.
29.7.
29.7.5 TWI Status Register Register Name: TWI_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 – 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed 0 = During the length of the current frame. 1 = When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable TWI).
29.7.6 TWI Interrupt Enable Register Register Name: TWI_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 – 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • NACK: Not Acknowledge 0 = No effect. 1 = Enables the corresponding interrupt. 29.7.
29.7.8 TWI Interrupt Mask Register Register Name: TWI_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 – 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • NACK: Not Acknowledge 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 29.
29.7.
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30. Two Wire Interface (TWI) SAM7S161/16 NOTE: This definition of the TWI does not pertain to SAM7S512/256/128/65/32/321. For SAM7S512/256/128/65/32/321, see Section 29. 30.1 Overview The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format.
30.3 Block Diagram Figure 30-1. Block Diagram APB Bridge TWCK PIO PMC MCK TWD Two-wire Interface TWI Interrupt 30.4 AIC Application Block Diagram Figure 30-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 30.4.1 I/O Lines Description Table 30-3.
TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: • Program the PIO controller to: – Dedicate TWD and TWCK as peripheral lines. – Define TWD and TWCK as open-drain. 30.5.2 Power Management • Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. 30.5.
• Multi-master receiver mode • Slave transmitter mode • Slave receiver mode These modes are described in the following chapters.
30.7 Master Mode 30.7.1 Definition The Master is the device which starts a transfer, generates a clock and stops it. 30.7.2 Application Block Diagram Figure 30-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 30.7.
Figure 30-6. Master Write with One Data Byte TWD S DADR W A DATA A P TXCOMP TXRDY STOP sent automaticaly (ACK received and TXRDY = 1) Write THR (DATA) Figure 30-7. Master Write with Multiple Data Byte S TWD DADR W A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) Figure 30-8.
nal address (IADR), the STOP bit must be set after the next-to-last data received. See Figure 30-10. For Internal Address usage see Section 30.7.6. Figure 30-9. Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 30-10.
•N Not Acknowledge • DADR Device Address • IADR Internal Address Figure 30-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address S TWD DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two bytes internal address S TWD DADR P One byte internal address S TWD DADR P Figure 30-12.
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30.7.7 Read-write Flowcharts The following flowcharts shown in Figure 30-14, Figure 30-15 on page 329, Figure 30-16 on page 330, Figure 3017 on page 331, Figure 30-18 on page 332 and Figure 30-19 on page 333 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 30-14.
Figure 30-15.
Figure 30-16.
Figure 30-17.
Figure 30-18.
Figure 30-19.
30.8 Multi-master Mode 30.8.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
Figure 30-20. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 30-21.
Figure 30-22.
30.9 Slave Mode 30.9.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 30.9.2 Application Block Diagram Figure 30-23. Slave Mode Typical Application Block Diagram VDD R Master Host with TWI Interface 30.9.
See Figure 30-24 on page 338. 30.9.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 30.9.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).
Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master.
30.9.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 30-28 on page 342 describes the clock synchronization in Read mode. Figure 30-28.
30.9.5.5 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 30-29 on page 343 describes the repeated start + reversal from Read to Write mode. Figure 30-29.
30.9.6 Read Write Flowcharts The flowchart shown in Figure 30-31 on page 344 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 30-31.
30.10 Two-wire Interface (TWI) User Interface Table 30-4.
30.10.1 Name: TWI Control Register TWI_CR Access: Write-only Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset.
30.10.
30.10.3 Name: Access: TWI Slave Mode Register TWI_SMR Read-write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.
30.10.4 Name: Access: TWI Internal Address Register TWI_IADR Read-write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
30.10.5 Name: Access: TWI Clock Waveform Generator Register TWI_CWGR Read-write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode.
30.10.6 Name: Access: TWI Status Register TWI_SR Read-only Reset Value: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame.
TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it.
NACK used in Slave Read mode: 0 = Each data byte has been correctly received by the Master. 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. • ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost.
30.10.
30.10.
30.10.
30.10.10 TWI Receive Holding Register Name: TWI_RHR Access: Read-only Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Master or Slave Receive Holding Data 30.10.
31. Universal Synchronous Asynchronous Receiver Transceiver (USART) 31.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
31.2 Block Diagram Figure 31-1.
Figure 31-2. SAM7S32/16 USART Block Diagram Peripheral DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS PMC MCK DIV SCK Baud Rate Generator MCK/DIV User Interface SLCK APB 31.3 Application Block Diagram Figure 31-3.
Figure 31-4. SAM7S32/16 Application Block Diagram IrLAP PPP Serial Driver Field Bus Driver EMV Driver IrDA Driver USART 31.4 RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers I/O Lines Description Table 31-1.
31.5 Product Dependencies 31.5.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
31.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.
Figure 31-5. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD SCK 0 1 2 16-bit Counter FIDI >1 3 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 31.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
Table 31-2. Baud Rate Example (OVER = 0) (Continued) Source Clock Expected Baud Rate Calculation Result CD Actual Baud Rate Error 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.
Figure 31-6. SAM7S512/256/128 Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 16-bit Counter 2 glitch-free logic 3 FIDI >1 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 31.6.1.4 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR.
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 31-4. Table 31-4. Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 31-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 31-5.
31.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled.
Figure 31-9. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 31.6.3.2 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line.
Figure 31-10. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 7 0 1 Start Rejection Figure 31-11.
31.6.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 31-13.
31.6.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 374. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd.
31.6.3.6 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
Table 31-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 31-7. Maximum Timeguard Length Depending on Baud Rate Baud Rate Bit time Timeguard Bit/sec µs ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 31.6.3.
Figure 31-16. Receiver Time-out Block Diagram TO Baud Rate Clock 1 D Clock Q 16-bit Time-out Counter 16-bit Value = STTTO Character Received Load Clear TIMEOUT 0 RETTO Table 31-8 gives the maximum time-out period for some standard baud rates. Table 31-8.
Figure 31-17. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 31.6.3.10 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0.
Figure 31-18. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 31.6.3.11 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR.
Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 31-20. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 RXDIS = 1 Write US_CR RTS RXBUFF Figure 31-21 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter.
CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 390 and “PAR: Parity Type” on page 392. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired.
31.6.4.4 Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1.
Figure 31-25. Connection to IrDA Transceivers USART IrDA Transceivers Receiver Demodulator RXD Transmitter Modulator TXD RX TX The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: • Disable TX and Enable RX • Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). • Receive data 31.6.5.
Figure 31-26. IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 0 1 1 0 0 1 1 0 1 TXD 3 16 Bit Period Bit Period 31.6.5.2 IrDA Baud Rate Table 31-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 31-10. IrDA Baud Rate Error Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.
31.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
31.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 31-28. Figure 31-28.
31.6.7 SAM7S512/256/128/64/321/161 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI.
31.6.8.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 31-31. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 31-31. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 31.6.8.
31.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 31-12.
31.7.1 Name: USART Control Register US_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS(1) 16 DTREN(1) 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – Note: 1. DTRDIS and DTREN do not pertain to the SAM7S32/16. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter.
Access Type: Read-write 31 – 30 – 29 – 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 – 22 – 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 15 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE • USART_MODE USART_MODE Mode of the USART 0 0 0 0 Normal 0 0 0 1 RS485 0 0 1 0 Hardware Handshaking 0 0 1 1 Modem (Reserved on SAM7S32/16) 0 1 0 0 IS07816 Protocol: T = 0 0 1 0 1 Reserved 0 1 1 0 IS07816 Protocol: T =
1: USART operates in Synchronous Mode. • PAR: Parity Type PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode • NBSTOP: Number of Stop Bits NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.
• INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.
31.7.3 Name: USART Interrupt Enable Register US_IER Access Type: Note: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC (1) 17 DSRIC (1) 16 RIIC (1) 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITERATION 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 1. DCDIC, DSRIC and RIIC do not pertain to the SAM7S32/16.
31.7.4 Name: USART Interrupt Disable Register US_IDR Access Type: Note: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC (1) 17 DSRIC (1) 16 RIIC (1) 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITERATION 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 1. DCDIC, DSRIC and RIIC do not pertain to the SAM7S32/16.
31.7.5 Name: USART Interrupt Mask Register US_IMR Access Type: Note: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC (1) 17 DSRIC(1) 16 RIIC (1) 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITERATION 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 1. DCDIC, DSRIC and RIIC do not pertain to the SAM7S32/16.
31.7.6 Name: USART Channel Status Register US_CSR Access Type: Note: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC (1) 17 DSRIC (1) 16 RIIC (1) 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITERATION 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 1. DCDIC, DSRIC and RIIC do not pertain to the SAM7S32/16.
• PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. • DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. • DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. • CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1.
31.7.7 Name: USART Receive Holding Register US_RHR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
31.7.8 Name: USART Transmit Holding Register US_THR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
31.7.
31.7.10 Name: USART Receiver Time-out Register US_RTOR Access Type: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
31.7.11 Name: USART Transmitter Timeguard Register US_TTGR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
31.7.12 Name: USART FI DI RATIO Register US_FIDI Access Type: Read-write Reset Value : 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.
31.7.13 Name: USART Number of Errors Register US_NER Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
31.7.14 Name: USART IrDA FILTER Register US_IF Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 408
32. Synchronous Serial Controller (SSC) 32.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
32.3 Application Block Diagram Figure 32-2. Application Block Diagram OS or RTOS Driver Power Management Interrupt Management Test Management SSC Serial AUDIO 32.4 Codec Time Slot Management Frame Management Line Interface Pin Name List Table 32-1.
The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins.
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 32.6.1.1 Clock Divider Figure 32-4.
The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 32-6.
32.6.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers.
The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 417. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected.
Figure 32-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) TD (Output) B1 BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 32-11.
32.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported.
compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. 32.6.
Table 32-3.
Figure 32-15. Receive Frame Format in Continuous Mode Start = Enable Receiver Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN RD Note: 1. STTDLY is set to 0. 32.6.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 32.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers.
Figure 32-17. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB Left Channel MSB Right Channel Figure 32-18.
Figure 32-19.
32.8 Syncrhronous Serial Controller (SSC) User Interface Table 32-4.
32.8.1 Name: SSC Control Register SSC_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive. If a character is currently being received, disables at end of current character reception.
32.8.2 Name: SSC Clock Mode Register SSC_CMR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DIV 3 2 DIV • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
32.8.
• CKG: Receive Clock Gating Selection CKG Receive Clock Gating 0x0 None, continuous clock 0x1 Receive Clock enabled only if RF Low 0x2 Receive Clock enabled only if RF High 0x3 Reserved • START: Receive Start Selection START Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
32.8.4 Name: SSC Receive Frame Mode Register SSC_RFMR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver.
• FSOS: Receive Frame Sync Output Selection FSOS Selected Receive Frame Sync Signal RF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Input-only Reserved Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
32.8.
CKG Transmit Clock Gating 0x1 Transmit Clock enabled only if TF Low 0x2 Transmit Clock enabled only if TF High 0x3 Reserved • START: Transmit Start Selection START Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
32.8.6 Name: SSC Transmit Frame Mode Register SSC_TFMR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 23 FSDEN 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit.
• FSOS: Transmit Frame Sync Output Selection FSOS Selected Transmit Frame Sync Signal TF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Input-only Reserved Undefined • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal.
32.8.7 Name: SSC Receive Holding Register SSC_RHR Access Type: 31 Read-only 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 32.8.
32.8.9 Name: SSC Receive Synchronization Holding Register SSC_RSHR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT • RSDAT: Receive Synchronization Data 32.8.
32.8.11 Name: SSC Receive Compare 0 Register SSC_RC0R Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 • CP0: Receive Compare Data 0 32.8.
32.8.13 Name: SSC Status Register SSC_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.
• RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register.
32.8.14 Name: SSC Interrupt Enable Register SSC_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt.
0 = No effect. 1 = Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt.
32.8.15 Name: SSC Interrupt Disable Register SSC_IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt.
0 = No effect. 1 = Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt.
32.8.16 Name: SSC Interrupt Mask Register SSC_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.
0 = The Receive Buffer Full Interrupt is disabled. 1 = The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled. • RXSYN: Rx Sync Interrupt Mask 0 = The Rx Sync Interrupt is disabled.
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 445
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 446
33. Timer Counter (TC) 33.1 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
33.2 Block Diagram Figure 33-1.
33.3 Pin Name List Table 33-3. TC pin list Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O 33.4 Product Dependencies 33.4.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 33.4.
33.5 Functional Description 33.5.1 TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 33-4 on page 463. 33.5.2 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
Figure 33-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK2 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 33-3.
33.5.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 33-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
• SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The channel can also be configured to have an external trigger.
MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST CLKI S R OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS INT Figure 33-5.
33.5.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TCCLKS TIOB MTIOB TIOA MTIOA Figur
33.5.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 33-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 33-8. RC Compare cannot be programmed to generate a trigger in this configuration.
33.5.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 33-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 33-10.
33.5.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 33-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-12.
33.5.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 33-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-14.
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 461
33.5.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
33.6 Timer Counter (TC) User Interface Table 33-4.
33.6.1 TC Block Control Register Register Name: TC_BCR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
33.6.
33.6.3 TC Channel Control Register Register Name: TC_CCRx [x=0..2] Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock.
33.6.4 TC Channel Mode Register: Capture Mode Register Name: TC_CMRx [x=0..
0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock.
33.6.5 TC Channel Mode Register: Waveform Mode Register Name: TC_CMRx [x=0..
0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • EEVT: External Event Selection EEVT Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note: 1.
ACPA Effect 0 1 set 1 0 clear 1 1 toggle • ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPC: RC Compare Effect on TIOB BCPC 0 Effect 0
BCPC Effect 0 1 set 1 0 clear 1 1 toggle • BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 472
33.6.6 TC Counter Value Register Register Name: TC_CVx [x=0..2] Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time. 33.6.7 TC Register A Register Name: TC_RAx [x=0..
33.6.8 TC Register B Register Name: TC_RBx [x=0..2] Access Type: Read-only if WAVE = 0, Read-write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time.
33.6.9 TC Register C Register Name: TC_RCx [x=0..2] Access Type: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time.
33.6.10 TC Status Register Register Name: TC_SRx [x=0..2] Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register.
• CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high.
33.6.11 TC Interrupt Enable Register Register Name: TC_IERx [x=0..2] Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt.
33.6.12 TC Interrupt Disable Register Register Name: TC_IDRx [x=0..2] Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect.
33.6.13 TC Interrupt Mask Register Register Name: TC_IMRx [x=0..2] Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled.
34. Pulse Width Modulation Controller (PWM) 34.1 overview The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
34.3 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 34-1. I/O Line Description Name Description Type PWMx PWM Waveform Output for channel x Output 34.4 Product Dependencies 34.4.1 I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function.
34.5.1 PWM Clock Generator Figure 34-2. Functional View of the Clock Generator Block Diagram MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A PREA clkA DIVA PWM_MR Divider B PREB clkB DIVB PWM_MR Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC).
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. 34.5.2 PWM Channel 34.5.2.1 Block Diagram Figure 34-3.
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (-------------------------------------------2 × X × CPRD ) MCK By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (------------------------------------------------------2 × CPRD × DIVA ) ( 2 × CPRD × DIVB ) or ------------------------------------------------------MCK MCK • the waveform duty cycle.
The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled. Figure 34-5.
34.5.3 PWM Controller Operations 34.5.3.1 Initialization Before enabling the output channel, this channel must have been configured by the software application: • Configuration of the clock generator if DIVA and DIVB are required • Selection of the clock for each channel (CPRE field in the PWM_CMRx register) • Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) • Configuration of the period for each channel (CPRD in the PWM_CPRDx register).
Figure 34-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level.
34.5.3.4 Interrupts Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register. 34.6 Pulse Width Modulation Controller (PWM) User Interface Table 34-2.
34.6.1 PWM Mode Register Register Name: PWM_MR Access Type: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 PREB 19 18 17 16 11 10 9 8 1 0 DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB CLKA, CLKB 0 CLKA, CLKB clock is turned off 1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
34.6.2 PWM Enable Register Register Name: PWM_ENA Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. 34.6.
34.6.4 PWM Status Register Register Name: PWM_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
34.6.5 PWM Interrupt Enable Register Register Name: PWM_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x. 34.6.
34.6.7 PWM Interrupt Mask Register Register Name: PWM_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled.
34.6.8 PWM Interrupt Status Register Register Name: PWM_ISR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
34.6.9 PWM Channel Mode Register Register Name: PWM_CMR[0..
34.6.10 PWM Channel Duty Cycle Register Register Name: PWM_CDTY[0..X-1] Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
34.6.11 PWM Channel Period Register Register Name: PWM_CPRD[0..X-1] Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 16 bits (internal channel counter size) are significant.
34.6.12 PWM Channel Counter Register Register Name: PWM_CCNT[0..X-1] Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register). • the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned. 34.6.
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 500
35. USB Device Port (UDP) 35.1 Overview The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is then notified that the device asks for a resume. This optional feature must be also negotiated with the host during the enumeration.
35.3 Product Dependencies For further details on the USB Device hardware implementation, see the specific Product Properties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are available from the product boundary. Two I/O lines may be used by the application: • One to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off.
35.4 Typical Connection Figure 35-2. Board Schematic to Interface USB Device Peripheral PIO 5V Bus Monitoring 27 K 47 K 3V3 PIO Pullup Control 0: Enable 1: Disable 1.5K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 330 K 35.4.1 330 K USB Device Transceiver The USB device transceiver is embedded in the product.
35.5 Functional Description 35.5.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 35-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.
35.5.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 35-3.
Figure 35-4. Control Read and Write Sequences Setup Stage Control Read Setup TX Data Stage Data OUT TX Setup Stage Control Write No Data Control Notes: Status Stage Data OUT TX Data Stage Setup TX Data IN TX Setup Stage Status Stage Setup TX Status IN TX Status IN TX Status Stage Data IN TX Status OUT TX 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID.
Figure 35-5. Setup Transaction Followed by a Data OUT Transaction Setup Received USB Bus Packets Setup PID Data Setup RXSETUP Flag Setup Handled by Firmware ACK PID Data OUT PID Data OUT Data Out Received NAK PID Data OUT ACK PID Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) FIFO (DPR) Content Data OUT PID XX Data Setup XX Data OUT 35.5.2.
Figure 35-6.
3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s UDP_ CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_ FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_ CSRx register is set.
3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_ CSRx register. 5. The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available by reading the endpoint’s UDP_ FDRx register. 6.
Figure 35-10.
Figure 35-11.
Figure 35-12. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 35-13.
35.5.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 35-14.
35.5.3.2 Entering Attached State When no device is connected, the USB DP and DM signals are tied to GND by 15 KΩ pull-down resistors integrated in the hub downstream ports. When a device is attached to a hub downstream port, the device connects a 1.5 KΩ pull-up resistor on DP. The USB bus line goes into IDLE state, DP is pulled up by the device 1.5 KΩ resistor to 3.3V and DM is pulled down by the 15 KΩ resistor of the host. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the and acknowledging the RXSUSP. 35.5.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set.
35.6 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register. Table 35-4.
35.6.1 UDP Frame Number Register Register Name: UDP_ FRM_NUM Access Type: Read-only 31 --- 30 --- 29 --- 28 --- 27 --- 26 --- 25 --- 24 --- 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
35.6.2 UDP Global State Register Register Name: UDP_ GLB_STAT Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 – 3 – 2 – 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state.
35.6.3 UDP Function Address Register Register Name: UDP_ FADDR Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.
35.6.4 UDP Interrupt Enable Register Register Name: UDP_ IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 – 11 SOFINT 10 – 9 8 RXRSM RXSUSP 7 6 5 4 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT • EP0INT: Enable Endpoint 0 Interrupt • EP1INT: Enable Endpoint 1 Interrupt • EP2INT: Enable Endpoint 2Interrupt • EP3INT: Enable Endpoint 3 Interrupt 0 = No effect.
35.6.5 UDP Interrupt Disable Register Register Name: UDP_ IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 – 11 SOFINT 10 – 9 8 RXRSM RXSUSP 7 6 5 4 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT • EP0INT: Disable Endpoint 0 Interrupt • EP1INT: Disable Endpoint 1 Interrupt • EP2INT: Disable Endpoint 2 Interrupt • EP3INT: Disable Endpoint 3 Interrupt 0 = No effect.
35.6.6 UDP Interrupt Mask Register Register Name: UDP_ IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 BIT12 11 SOFINT 10 – 9 8 RXRSM RXSUSP 7 6 5 4 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT • EP0INT: Mask Endpoint 0 Interrupt • EP1INT: Mask Endpoint 1 Interrupt • EP2INT: Mask Endpoint 2 Interrupt • EP3INT: Mask Endpoint 3 Interrupt 0 = Corresponding Endpoint Interrupt is disabled.
35.6.7 UDP Interrupt Status Register Register Name: UDP_ ISR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 – 9 8 RXRSM RXSUSP 7 6 5 4 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT • EP0INT: Endpoint 0 Interrupt Status • EP1INT: Endpoint 1 Interrupt Status • EP2INT: Endpoint 2 Interrupt Status • EP3INT: Endpoint 3 Interrupt Status 0 = No Endpoint0 Interrupt pending.
• SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence.
35.6.8 UDP Interrupt Clear Register Register Name: UDP_ ICR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 – 9 RXRSM 8 RXSUSP 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt.
35.6.9 UDP Reset Endpoint Register Register Name: UDP_ RST_EP Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 EP3 2 EP2 1 EP1 0 EP0 • EP0: Reset Endpoint 0 • EP1: Reset Endpoint 1 • EP2: Reset Endpoint 2 • EP3: Reset Endpoint 3 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.
35.6.10 UDP Endpoint Control and Status Register Register Name: UDP_ CSRx [x = 0..
This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0. 1 = A data packet has been received, it has been stored in the FIFO's Bank 0.
Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. • TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device.
• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO’s Bank 1. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1.
Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. • EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero).
35.6.11 UDP FIFO Data Register Register Name: UDP_ FDRx [x = 0..Y] Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_ CSRx register is the number of bytes to be read from the FIFO (sent by the host).
35.6.12 UDP Transceiver Control Register Register Name: UDP_ TXVC Access Type: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register.
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 536
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 537
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 538
36. Analog-to-Digital Converter (ADC) 36.1 Overview The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital conversions of 8 analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
36.3 Signal Description Table 36-1. ADC Pin Description Pin Name Description ADVREF Reference voltage AD0 - AD7 Analog input channels ADTRG External trigger 36.4 Product Dependencies 36.4.1 Power Management The ADC Controller clock (MCK) is always clocked. 36.4.2 Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the ADC interrupt requires the AIC to be programmed first. 36.4.
36.5 Functional Description 36.5.1 Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the “ADC Mode Register” on page 548 and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F).
36.5.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt.
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (ADC_SR). In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in ADC_SR. The OVRE and GOVRE flags are automatically cleared when ADC_SR is read. Figure 36-3.
36.5.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR).
36.5.7 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register ADC_MR. In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC.
36.6 Analog-to-Digital Converter (ADC) User Interface Table 36-2.
36.6.1 ADC Control Register Register Name: ADC_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 START 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion.
36.6.2 ADC Mode Register Register Name: ADC_MR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 23 – 22 21 20 19 STARTUP 15 14 13 12 26 25 24 18 17 16 11 10 9 8 3 2 TRGSEL 1 0 TRGEN SHTIM PRESCAL 7 – 6 – 5 SLEEP 4 LOWRES • TRGEN: Trigger Enable TRGEN Selected TRGEN 0 Hardware triggers are disabled. Starting a conversion is only possible by software. 1 Hardware trigger selected by TRGSEL field is enabled.
• PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 ) • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock • SHTIM: Sample & Hold Time Sample & Hold Time = SHTIM/ADCClock SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 549
36.6.3 ADC Channel Enable Register Register Name: ADC_CHER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel. 36.6.
36.6.5 ADC Channel Status Register Register Name: ADC_CHSR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
36.6.6 ADC Status Register Register Name: ADC_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RXBUFF 18 ENDRX 17 GOVRE 16 DRDY 15 OVRE7 14 OVRE6 13 OVRE5 12 OVRE4 11 OVRE3 10 OVRE2 9 OVRE1 8 OVRE0 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished. 1 = Corresponding analog channel is enabled and conversion is complete.
36.6.7 ADC Last Converted Data Register Register Name: ADC_LCDR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 LDATA 0 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. 36.6.
36.6.
36.6.
36.6.11 ADC Channel Data Register Register Name: ADC_CDRx Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 DATA 0 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
37. SAM7S Electrical Characteristics 37.1 Absolute Maximum Ratings Table 37-1. Absolute Maximum Ratings* Operating Temperature (Industrial) ...... ..........-40° C to + 85° C Storage Temperature ..... ...............................-60°C to + 150°C Voltage on Input Pins with Respect to Ground ..... ..............................-0.3V to + 5.5V Maximum Operating Voltage (VDDCORE, and VDDPLL)................. ..............................2.
37.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C unless otherwise specified. Table 37-2. DC Characteristics Symbol Parameter VVDDCORE DC Supply Core VVDDPLL DC Supply PLL VVDDIO DC Supply I/Os VVDDFLASH DC Supply Flash VIL Input Low-level Voltage VIH Input High-level Voltage VOL VOH ILEAK Conditions Max Units 1.65 1.95 V 1.65 1.95 V 3.0 3.6 V 1.65 1.95 V 3.0 3.6 V VVDDIO from 3.0V to 3.6V -0.
Table 37-2. ISC ISC ISC IO DC Characteristics (Continued) Static Current (SAM7S64/321/32/ 161/16) Static Current (SAM7S256/128) Static Current (SAM7S512) Output Current On VVDDCORE = 1.85V, MCK = 500Hz TA = 25°C 4.0 All inputs driven at 1 (including TMS, TDI, TCK, NRST) Flash in standby mode All peripherals off. TA = 85°C 25 100 On VVDDCORE = 1.85V, MCK = 500Hz TA = 25°C 4.
Table 37-4. Brownout Detector Characteristics Symbol Parameter Conditions Min Typ Max Units VBOT- Threshold Level Falling edge 1.65 1.68 1.71 V VHYST Hysteresis VHYST = VBOT+ - VBOT- 50 65 mV BOD on (GPNVM0 bit active) 12 18 µA IDD Current Consumption 1 µA TSTART Startup Time 200 µs BOD off (GPNVM0 bit inactive) Table 37-5. DC Flash Characteristics SAM7S64/321/32/161/16 Symbol Parameter TPU Power-up delay Table 37-6. Max Units 45 µS @25°C onto VDDCORE = 1.
• Power consumption of power supply in two different modes: Active and ultra Low-power. • Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 37.3.1 Power Consumption Versus Modes The values in Table 37-7 and Table 37-8 on page 566 are measured values of the power consumption with operating conditions as follows: • VDDIO = VDDIN = VDDFLASH= 3.3V • VDDCORE = VDDPLL = 1.
These figures represent the power consumption typically measured on the power supplies.. Table 37-7. Power Consumption for Different Modes Mode Conditions Active, running out of Flash, 8 MHz (SAM7S64/321/32/161/16) Active, running out of Flash, 8 MHz (SAM7S512/256/128) Active, running out of Flash, 16 MHz (SAM7S64/321/32/161/16) Active, running out of Flash, 16 MHz (SAM7S512/256/128) Consumption Unit Voltage regulator is on. Brown Out Detector is activated. Flash is read. PLL is activated.
Table 37-7. Power Consumption for Different Modes Mode Conditions Active, running out of Flash, 32 MHz (SAM7S64/321/32/161/16) Active, running out of Flash, 32 MHz (SAM7S512/256/128) Active, running out of Flash, 48 MHz (SAM7S64/321/32/161/16) Active, running out of Flash, 32 MHz (SAM7S512/256/128) Consumption Unit Voltage regulator is on. Brown Out Detector is activated. Flash is read. PLL is activated. ARM Core clock is 32 MHz. Analog-to-Digital Converter activated.
Table 37-7. Power Consumption for Different Modes Mode Conditions Active, running out of Flash, 50 MHz (SAM7S64/321/32/161/16) Active, running out of Flash, 50 MHz (SAM7S512/256/128) Active, running out of Flash, 55 MHz (SAM7S64/321/32/161/16) Active, running out of Flash, 55 MHz (SAM7S512/256/128) Consumption Unit Voltage regulator is on. Brown Out Detector is activated. Flash is read. PLL is activated. ARM Core clock is 50 MHz. Analog-to-Digital Converter activated.
Table 37-7. Power Consumption for Different Modes Mode Conditions Active, Running out of SRAM, 1.1MHz (SAM7S64/321/32/161/16) Active, Running out of SRAM, 1MHz (SAM7S512/256/128) Ultra low power Note: Consumption Unit Voltage regulator is on. Brown Out Detector is activated. Flash is in standby mode. PLL is de-activated. Main oscillator is activated. ARM Core clock is 1.1 MHz. Running out of SRAM Analog-to-Digital Converter activated. All peripheral clocks activated. USB transceiver enabled.
37.3.2 Peripheral Power Consumption in Active Mode Table 37-8. Power Consumption on VDDCORE(1) Peripheral Consumption (Typ) PIO Controller 12 USART 28 UDP 20 PWM 16 TWI 5 SPI 16 SSC 32 Timer Counter Channels 6 ARM7TDMI 160 System Peripherals (SAM7S512/256/128) 190 System Peripherals (SAM7S64/321/32/161/16) 140 Note: Unit µA/MHz 1. Note: VDDCORE = 1.
37.4 Crystal Oscillators Characteristics 37.4.1 RC Oscillator Characteristics Table 37-9. RC Oscillator Characteristics Symbol Parameter Conditions 1/(tCPRC) RC Oscillator Frequency VDDPLL = 1.65V Duty Cycle Min Typ Max Unit 22 32 42 kHz 45 50 55 % tST Startup Time VDDPLL = 1.65V 75 µs IOSC Current Consumption After Startup Time 1.
37.4.2 Main Oscillator Characteristics Table 37-10. Main Oscillator Characteristics Symbol Parameter Conditions 1/(tCPMAIN) Crystal Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) CL (6) Equivalent Load Capacitance Min Typ Max Unit 3 16 20 MHz Integrated Load Capacitance ((XIN or XOUT)) 34 40 46 pF Integrated Load Capacitance (XIN and XOUT in series) 17 20 23 pF 30 50 70 % Duty Cycle tST Startup Time VDDPLL = 1.
37.4.3 Crystal Characteristics Table 37-11. Crystal Characteristics Symbol Parameter Conditions ESR Equivalent Series Resistor Rs Fundamental @3 MHz Fundamental @8 MHz Fundamental @16 MHz Fundamental @20 MHz CM CSHUNT 37.4.4 Min Typ Max Unit 200 100 80 50 W Motional capacitance 8 fF Shunt capacitance 7 pF XIN Clock Characteristics Table 37-12. XIN Clock Electrical Characteristics Symbol Parameter 1/(tCPXIN) XIN Clock Frequency (1) XIN Clock Period (1) 20.
37.5 PLL Characteristics Table 37-13. Phase Lock Loop Characteristics Symbol Parameter Conditions Min FOUT Output Frequency: SAM7S64/32/312/161/16 Field out of CKGR_PLL is: FOUT Output Frequency: SAM7S512/256/128 Field out of CKGR_PLL is: FIN Input Frequency IPLL Current Consumption Typ Max Unit 00 80 160 MHz 10 150 200 MHz 00 80 160 MHz 10 150 180 MHz 1 32 MHz Active mode 4 mA Standby mode 1 µA Note: Startup time depends on PLL RC filter.
Table 37-15. I/O Characteristics (Continued) Symbol PulseminLI02 FreqMaxI03 PulseminHI03 PulseminLI03 Notes: Parameter Pin Group 2 (2) Low Level Pulse Width Pin Group 3 (3) frequency Pin Group 3 (3) High Level Pulse Width Pin Group 3 (3) Low Level Pulse Width Conditions Min Max Units 3.3V domain (4) 20 ns 1.8V domain (5) 36 ns 3.3V domain (4) 30 MHz 1.8V domain (5) 11 MHz 3.3V domain (4) 16.6 ns 1.8V domain (5) 45 ns 3.3V domain (4) 16.6 ns 45 ns 1.8V domain (5) 1.
37.8 USB Transceiver Characteristics 37.8.1 Electrical Characteristics Table 37-16. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit 0.8 V Input Levels VIL Low Level VIH High Level VDI Differential Input Sensitivity VCM Differential Input Common Mode Range CIN Transceiver capacitance Capacitance to ground on each line I Hi-Z State Data Line Leakage 0V < VIN < 3.
Figure 37-3.
37.9 ADC Characteristics Table 37-18. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency Min Max Units 10-bit resolution mode 5 MHz ADC Clock Frequency 8-bit resolution mode 8 MHz Startup Time Return from Idle Mode 20 µs Track and Hold Acquisition Time Typ 600 ns Conversion Time ADC Clock = 5 MHz 2 µs Conversion Time ADC Clock = 8 MHz 1.
Table 37-21. Transfer Characteristics (Continued) Parameter Conditions Min Typ Max Units Offset Error ±2 LSB Gain Error ±2 LSB Absolute Accuracy ±4 LSB For more information on data converter terminology, please refer to the application note: Data Converter Terminology, Atmel lit° 6022.
37.10 AC Characteristics 37.10.1 SPI Characteristics Figure 37-4. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI0 SPI1 MISO SPI2 MOSI Figure 37-5. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI3 SPI4 MISO SPI5 MOSI Figure 37-6.
Figure 37-7. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI9 MISO SPI10 SPI11 MOSI Table 37-22.
37.10.2 SSC Characteristics Figure 37-8. SSC Transmitter, TK and TF in output TK (CKI =0) TK (CKI =1) SSC0 TF/TD Figure 37-9. SSC Transmitter, TK in input and TF in output TK (CKI =0) TK (CKI =1) SSC1 TF/TD Figure 37-10.
Figure 37-11. SSC Transmitter, TK and TF in input TK (CKI=1) TK (CKI=0) SSC5 SSC6 TF SSC7 TD Figure 37-12. SSC Receiver RK and RF in input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 37-13.
Figure 37-14. SSC Receiver, RK and RF in output RK (CKI=1) RK (CKI=0) SSC12 SSC11 RD SSC13 RF Figure 37-15. SSC Receiver, RK in output and RF in input RK (CKI=0) RK (CKI=1) SSC11 SSC12 RF/RD Table 37-23. SSC Timings Symbol Parameter Conditions Min Max Units 3.3V domain 0(2) 12.5(2) ns 1.
Table 37-23. SSC Timings (Continued) Symbol Parameter SSC7(1) TK edge to TF/TD (TK input, TF input) Conditions Min Max 3.3V domain 6 (+3*tCPMCK)(1)(2) 29.5 (+3*tCPMCK)(1)(2) 1.
37.10.3 Embedded Flash Characteristics The maximum operating frequency is given in Table 37-24 but is limited by the Embedded Flash access time when the processor is fetching code out of it. Table 37-24 gives the device maximum operating frequency depending on the FWS field of the MC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory. Table 37-24.
37.10.4 JTAG/ICE Timings 37.10.4.1 . ICE Interface Signals Table 37-26. ICE Interface Timing Specification Symbol Parameter Conditions TCK Low Half-period (1) 51 ns TCK High Half-period (1) 51 ns ICE2 TCK Period (1) 102 ns ICE3 TDI, TMS, Setup before TCK High (1) 0 ns TDI, TMS, Hold after TCK High (1) 3 ns TDO Hold Time (1) 13 ns TCK Low to TDO Valid (1) ICE0 ICE1 ICE4 ICE5 ICE6 Note: Min Max Units 20 ns 1. VVDDIO from 3.0V to 3.
37.10.4.2 . JTAG Interface Signals Table 37-27. JTAG Interface Timing Specification Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Note: Parameter Conditions Min TCK Low Half-period (1) Max 6.5 ns TCK High Half-period (1) 5.
38. Mechanical Characteristics 38.1 Package Drawings The SAM7S series devices are available in LQFP and QFN package types. 38.2 LQFP Packages Figure 38-1.
Table 38-1. 48-lead LQFP Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC E 9.00 BSC 0.354 BSC E1 7.00 BSC 0.276 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
Table 38-2. Symbol 64-lead LQFP Package Dimensions (in mm) Millimeter Inch Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.383 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
38.3 QFN Packages Figure 38-2.
Table 38-6. 48-pad QFN Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 090 – – 0.035 A1 – – 0.050 – – 0.002 A2 – 0.65 0.70 – 0.026 0.028 A3 b 0.20 REF 0.18 D D2 0.20 0.008 REF 0.23 0.007 7.00 bsc 5.45 E 5.60 0.008 0.009 0.276 bsc 5.75 0.215 7.00 bsc 0.220 0.226 0.276 bsc E2 5.45 5.60 5.75 0.215 0.220 0.226 L 0.35 0.40 0.45 0.014 0.016 0.018 e R 0.50 bsc 0.09 – 0.020 bsc – 0.
Figure 38-3.
Table 38-7. 64-pad QFN Package Dimensions (in mm) Millimeter Symbol Inch Min Nom Max Min Nom Max A – – 090 – – 0.035 A1 – – 0.05 – – 0.001 A2 – 0.65 0.70 – 0.026 0.028 A3 0.20 REF b 0.23 D 0.25 0.008 REF 0.28 0.009 0.010 9.00 bsc D2 6.95 E 7.10 7.25 0.274 7.10 7.25 0.274 0.40 0.45 0.014 0.280 9.00 bsc E2 6.95 L 0.35 e 0.125 – 0.285 0.354 bsc 0.50 bsc R 0.011 0.354 bsc 0.280 0.285 0.016 0.018 0.020 bsc – 0.
38.4 Soldering Profile Table 38-11 gives the recommended soldering profile from J-STD-020C. Table 38-11. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3° C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5° C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260° C Ramp-down Rate 6° C/sec. max. Time 25° C to Peak Temperature 8 min. max.
39. SAM7S Ordering Information Table 39-1.
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 594
40. Errata 40.1 Marking All devices are marked with the Atmel logo and the ordering code.
40.2 Errata Summary by Product and Revision or Manufacturing Number Table 40-1.
Table 40-1.
“SAM7S256 Errata - Revision B Parts” on page 634 “SAM7S256 Errata - Revision C Parts” on page 642 “SAM7S256 Errata - Revision D Parts” on page 644 “SAM7S128 Errata - Manufacturing Number 58818C” on page 646 “SAM7S128 Errata - Revision A Parts” on page 656 “SAM7S128 Errata - Revision B Parts” on page 666 “SAM7S128 Errata - Revision C Parts” on page 674 “SAM7S128 Errata - Revision D Parts” on page 676 “SAM7S64 Errata - Manufacturing Number 58814G” on page 678 “SAM7S64 Errata - Revision A Parts” on page 688 “S
40.4 SAM7S512 Errata - Revision A Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S512 Revision A chip ID is: 0x270B 0A40. 40.4.1 Analog-to-Digital Converter (ADC) 40.4.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.4.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.4.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.4.1.
The maximum operating frequency with one Wait State (FWS = 1) is 48.1 MHz (instead of 55 MHz). Above 48.1 MHz and until 55 MHz, two Wait States (FWS = 2) are required. Problem Fix/Workaround Set the number of Wait States (FWS) according to the frequency requirements described in this errata. 40.4.3 Parallel Input/Output Controller (PIO) 40.4.3.
40.4.4.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational. Problem Fix/Workaround Do not write 0 in the period register. 40.4.4.3 PWM: Counter Start Value In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1. Problem Fix/Workaround None. 40.4.4.
40.4.6.3 SPI: LASTXFER (Last Transfer) Behavior In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on the data written in the SPI_TDR when the TX_EMPTY flag is set. If for example, the PDC writes a “1” in the bit 24 (LASTXFER bit) of the SPI_TDR, the chip select will rise as soon as the TXEMPTY flag is set. Problem Fix/Workaround Use the CS in PIO mode when PDC mode is required and CS has to be maintained between transfers. 40.4.6.
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1. If all chip selects are configured with Baudrate = 1, the issue does not appear. 40.4.7 Synchronous Serial Controller (SSC) 40.4.7.1 SSC: Periodic Transmission Limitations in Master Mode If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 40.4.7.
None. 40.4.8.2 TWI: Software Reset when a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 40.4.8.3 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
40.4.9.3 USART: XOFF Character Bad Behavior The XOFF character is sent only when the receive buffer is detected full. While the XOFF is being sent, the remote transmitter is still transmitting. As only one Holding register is available in the receiver, characters will be lost in reception. This makes the software handshaking functionality ineffective. Problem Fix/Workaround None. 40.4.9.
40.5.1.4 ADC: Possible Skip on DRDY when Disabling a Channel DRDY does not rise when disabling channel “y” at the same time as an end of “x” channel conversion, although data is stored into CDRx and LCDR. Problem Fix/Workaround None. 40.5.1.5 ADC: GOVRE Bit is not Updated Read of the Status Register at the same instant as an end of conversion leads to skipping the update of the GOVRE (general overrun) flag. GOVRE is neither reset nor set.
Problem Fix/Workaround Do not take into account the EOC of a disabled channel 40.5.1.10 ADC: Spurious Clear of EOC Flag If “x” and “y” are two successively converted channels and “z” is yet another enabled channel (“z” being neither “x” nor “y”), reading CDR on channel “z” at the same instant as an end of conversion on channel “y” automatically clears EOC[x] instead of EOC[z]. Problem Fix/Workaround None. 40.5.1.
40.5.3.2 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31 When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.45 V This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V and 25 µA at 1.8V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.5 µA 45 µA I Leakage at 1.
Do not set PWM_CDTYx at 0 in center aligned mode. Do not set PWM_CDTYx at 0 or 1 in left aligned mode. 40.5.4.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
40.5.6.5 SPI: Chip Select and Fixed Mode In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip select 0, the output spi_size sampled by the PDC will depend on the field, BITS (Bits per Transfer) of SPI_CSR0 register, whatever the selected Chip select is.
40.5.7.2 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge (rising or falling) of synchro has a Start Delay equal to zero. Problem Fix/Workaround None. 40.5.7.
Problem Fix/Workaround The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before disabling the TWI. 40.5.8.4 TWI: NACK Status Bit Lost During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set. Problem Fix/Workaround The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission is not completed.
The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP condition is taken into account by the receiver state machine. After this STOP condition, as there is no valid data, the receiver state machine will go in idle mode and enable the RXBRK flag. 40.5.9.5 USART: DCD is active High instead of Low The DCD signal is active at High level in the USART Modem Mode. DCD should be active at Low level. Problem Fix/Workaround Add an inverter. 40.
40.6.2.5 ADC: GOVRE Bit is not Updated Read of the Status Register at the same instant as an end of conversion leads to skipping the update of the GOVRE (general overrun) flag. GOVRE is neither reset nor set. For example, if reading the status while an end of conversion is occurring and: 1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun condition but the GOVRE flag is not reset. 2.
40.6.2.10 ADC: Spurious Clear of EOC Flag If “x” and “y” are two successively converted channels and “z” is yet another enabled channel (“z” being neither “x” nor “y”), reading CDR on channel “z” at the same instant as an end of conversion on channel “y” automatically clears EOC[x] instead of EOC[z]. Problem Fix/Workaround None. 40.6.2.11 ADC: Sleep Mode If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after a conversion occurs.
40.6.5 Parallel Input/Output Controller (PIO) 40.6.5.1 PIO: Leakage on PA17 - PA20 When PA17, PA18, PA19 or PA20 (the I/O lines multiplexed with the analog inputs) are set as digital inputs with pull-up disabled, the leakage can be 9 µA in worst case and 90 nA in typical case per I/O when the I/O is set externally at low level. Problem Fix/Workaround Set the I/O to VDDIO by internal or external pull-up. 40.6.5.
– PLL Clock to Main Clock or – Main Clock to PLL Clock or – Main Clock to Slow Clock And 2. Program code is being executed out of flash, or a transition is occurring on PA1, either as an input or output. Note: This issue does not occur when transitioning from slow clock to main clock or from slow clock to PLL clock.
Problem Fix/Workaround Do not disable a channel before completion of one period of the selected clock. 40.6.8 Real Time Timer (RTT) 40.6.8.1 RTT: Possible Event Loss when Reading RTT_SR If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event. Problem Fix/Workaround The software must handle the RTT event as an interrupt and should not poll RTT_SR. 40.6.8.
40.6.9.5 SPI: Baudrate Set to 1 When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency) and when the BITS field of the SPI_CSR register (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse will be generated on output SPCK. Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1. Problem Fix/Workaround None. 40.6.9.6 SPI: Disable In Slave Mode The SPI disable is not possible in slave mode.
Problem Fix/Workaround The data need to be delayed for one bit clock period with an external assembly. In the following schematic, TD, TK and NRST are SAM7S signals, TXD is the delayed data to connect to the device. 40.6.11 Two-wire Interface (TWI) 40.6.11.1 TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191 Problem Fix/Workaround None. 40.6.11.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR. 40.6.11.5 TWI: Possible Receive Holding Register Corruption When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs. Problem Fix/Workaround The user must be sure that received data is read before transmitting any new data. 40.6.
40.6.13 Voltage Regulator 40.6.13.1 Voltage Regulator: Current Consumption in Deep Mode Current consumption in Deep Mode is maximum 60 µA instead of 25 µA. Due to current rejection from VDDIN to VDDCORE, the current consumption in Deep Mode cannot be guaranteed. Instead, 60 µA is guaranteed whatever the condition. Problem Fix/Workaround None. 40.6.13.2 Voltage Regulator: Load Versus Temperature Maximum load is 50 mA at 85 °C (instead of 100 mA). Maximum load is 100 mA at 70°C. Problem Fix/Workaround None.
40.7 SAM7S256 Errata - Revision A Parts Refer to Section 40.1 “Marking” on page 595. Important: Section 40.7.13.1 ”WDT: The Watchdog Timer May Lock the Device in a Reset State” 40.7.1 Chip ID 40.7.1.1 Wrong Chip ID Value The Chip ID is 0x270D 0940 instead of 0x270B 0940. Problem Fix/Workaround None. 40.7.2 Analog-to-Digital Converter (ADC) 40.7.2.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register).
40.7.2.6 ADC: GOVRE Bit is not Set when Reading CDR When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on channel “x” with the following conditions: • EOC[x] already active, • DRDY already active, • GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.7.2.
40.7.3 Non Volatile Memory Bits (NVM Bits) 40.7.3.1 NVM Bits: Write/Erase Cycles Number The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit. This maximum number of write/erase cycles is not applicable to 256 KB Flash memory, it remains at 10K for the Flash memory. Problem Fix/Workaround None. 40.7.4 Parallel Input/Output Controller (PIO) 40.7.4.
40.7.5 Power Management Controller (PMC) 40.7.5.1 PMC: Slow Clock Selected in PMC and a Transition Occurs on PA1 Under certain rare circumstances, when CSS = 00 in PMC_MCKR, and PA1 is set as an input and a transition occurs on PA1, device malfunction might occur. Problem Fix/Workaround Do not transition PA1 as an input when CSS = 00 in PMC_MCKR. 40.7.5.2 PMC: Programming CSS in PMC_MCKR Register Under certain rare circumstances, reprogramming the CSS value in the PMC_MCKR register (i.
None. 40.7.6.4 PWM: Constraints on Duty Cycle Value Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode may change the polarity of the signal. Problem Fix/Workaround Do not set PWM_CDTYx at 0 in center aligned mode. Do not set PWM_CDTYx at 0 or 1 in left aligned mode. 40.7.6.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register.
Problem Fix/Workaround In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers. 40.7.8.4 SPI: Chip Select and Fixed Mode In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip select 0, the output spi_size sampled by the PDC will depend on the field, BITS (Bits per Transfer) of SPI_CSR0 register, whatever the selected Chip select is.
None. 40.7.9.2 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge (rising or falling) of synchro has a Start Delay equal to zero. Problem Fix/Workaround None. 40.7.9.
40.7.10.3 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset. Problem Fix/Workaround The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before disabling the TWI. 40.7.10.
Constraints on the transmitter device connected to the SAM7S USART receiver side: The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP condition is taken into account by the receiver state machine. After this STOP condition, as there is no valid data, the receiver state machine will go in idle mode and enable the RXBRK flag. 40.7.11.5 USART: DCD is active High instead of Low The DCD signal is active at High level in the USART Modem Mode. DCD should be active at Low level.
Problem Fix/Workaround Two workarounds are possible. 1. Either do not use the Watchdog Timer with the Watchdog fault Interrupt enabled (WDFIEN set at 1), 2. or set WDD to 0xFFF and in addition use only one of the following values for WDV: 0xFFF, 0xDFF, 0xBFF, 0x9FF, 0x7FF, 0x77F, 0x6FF, 0x67F, 0x5FF, 0x57F, 0x4FF, 0x47F, 0x3FF, 0x37F, 0x2FF, 0x27F, 0x1FF, 0x1BF, 0x17F, 0x13F, 0x0FF, 0x0DF, 0x0BF, 0x09F, 0x07F, 0x06F, 0x05F, 0x04F, 0x03F, 0x037, 0x02f, 0x027, 0x01F, 0x01B, 0x017, 0x013 and 0x00F.
40.8 SAM7S256 Errata - Revision B Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S256 Revision B chip ID is 0x270B 0941. 40.8.1 Analog-to-Digital Converter (ADC) 40.8.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.8.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.8.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.8.1.
This maximum number of write/erase cycles is not applicable to 256 KB Flash memory, it remains at 10K for the Flash memory. Problem Fix/Workaround None. 40.8.3 Parallel Input/Output Controller (PIO) 40.8.3.1 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31 When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.
Problem Fix/Workaround None. 40.8.4.4 PWM: Constraints on Duty Cycle Value Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode may change the polarity of the signal. Problem Fix/Workaround Do not set PWM_CDTYx at 0 in center aligned mode. Do not set PWM_CDTYx at 0 or 1 in left aligned mode. 40.8.4.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register.
40.8.6.4 SPI: SPCK Behavior in Master Mode SPCK pin can toggle out before the first transfer in Master Mode. Problem Fix/Workaround In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers. 40.8.6.
40.8.7 Synchronous Serial Controller (SSC) 40.8.7.1 SSC: Periodic Transmission Limitations in Master Mode If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 40.8.7.2 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge (rising or falling) of synchro has a Start Delay equal to zero. Problem Fix/Workaround None. 40.8.7.
40.8.8.2 TWI: Software Reset when a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 40.8.8.3 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
None. 40.8.9.4 USART: RXBRK Flag Error in Asynchronous Mode In receiver mode, when there are two consecutive characters (without timeguard in between), RXBRK is not taken into account. As a result, the RXBRK flag is not enabled correctly and the frame error flag is set. Problem Fix/Workaround Constraints on the transmitter device connected to the SAM7S USART receiver side: The transmitter may use the timeguard feature or send two STOP conditions.
40.9 SAM7S256 Errata - Revision C Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S256 Revision C chip ID is 0x270B 0942. 40.9.1 Embedded Flash Controller (EFC) 40.9.1.1 EFC: Embedded Flash Access Time 1 The embedded Flash maximum access time is 20 MHz (instead of 30 MHz) at zero Wait State (FWS = 0). The maximum operating frequency with one Wait State (FWS = 1) is 48.1 MHz (instead of 55 MHz). Above 48.1 MHz and up to 55 MHz, two Wait States (FWS = 2) are required.
40.9.3.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational. Problem Fix/Workaround Do not write 0 in the period register. 40.9.3.3 PWM: Counter Start Value In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1. Problem Fix/Workaround None. 40.9.4 Real Time Timer (RTT) 40.9.4.
40.10 SAM7S256 Errata - Revision D Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S256 Revision D chip ID is 0x270B0943. 40.10.1 Embedded Flash Controller (EFC) 40.10.1.1 EFC: Embedded Flash Access Time 1 The embedded Flash maximum access time is 20 MHz (instead of 30 MHz) at zero Wait State (FWS = 0). The maximum operating frequency with one Wait State (FWS = 1) is 48.1 MHz (instead of 55 MHz). Above 48.1 MHz and up to 55 MHz, two Wait States (FWS = 2) are required.
40.10.3.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational. Problem Fix/Workaround Do not write 0 in the period register. 40.10.3.3 PWM: Counter Start Value In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1. Problem Fix/Workaround None. 40.10.4 Real Time Timer (RTT) 40.10.4.
40.11 SAM7S128 Errata - Manufacturing Number 58818C Refer to Section 40.1 “Marking” on page 595. Important: Section 40.11.14.1 ”WDT: The Watchdog Timer May Lock the Device in a Reset State” 40.11.1 Chip ID 40.11.1.1 Wrong Chip ID Value The Chip ID is 0x270C0740 instead of 0x270A0740. Problem Fix/Workaround None. 40.11.2 Analog-to-Digital Converter (ADC) 40.11.2.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register).
40.11.2.6 ADC: GOVRE Bit is not Set when Reading CDR When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on channel “x” with the following conditions: • EOC[x] already active, • DRDY already active, • GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.11.2.
40.11.3 Master Clock (MCK) 40.11.3.1 MCK: Limited Master Clock Frequency Ranges If the Flash is operating without wait states, the frequency of the Master Clock MCK must be lower than 3 MHz or higher than 19 MHz. If the Flash is operating with one wait state, the frequency of the Master Clock MCK must be lower than 3 MHz or higher than 19 MHz. If the Flash is operating with two wait states, the frequency of the Master Clock MCK must be lower than 3 MHz or higher than 25 MHz.
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V and 25 µA at 1.8V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.5 µA 45 µA I Leakage at 1.8V 1 µA 25 µA Problem Fix/Workaround It is recommended to use an external pull-up if needed. 40.11.5.
40.11.7 Pulse Width Modulation Controller (PWM) 40.11.7.1 PWM: Update when PWM_CCNTx = 0 or 1 If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is directly modified when writing the Channel Update Register. Problem Fix/Workaround Check the Channel Counter Register before writing the update register. 40.11.7.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational.
40.11.9 Serial Peripheral Interface (SPI) 40.11.9.1 SPI: Bad tx_ready behavior when CSAAT = 1 and SCBR = 1 If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been transferred in the shifter. This can imply for example, that the second data is sent twice. Problem Fix/Workaround Do not use the combination CSAAT = 1 and SCBR = 1. 40.11.9.
This occurs using SPI with the following conditions: • Master Mode • CPOL = 1 and NCPHA = 0 • Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1 • Transmitting with the slowest chip select and then with the fastest one, then an additional on output SPCK during the second transfer.
40.11.11 Two-wire Interface (TWI) 40.11.11.1 TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 40.11.11.2 TWI: Software Reset When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 40.11.11.
40.11.11.5 TWI: Possible Receive Holding Register Corruption When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs. Problem Fix/Workaround The user must be sure that received data is read before transmitting any new data. 40.11.12 USART: Universal Synchronous Asynchronous Receiver Transmitter 40.11.12.
Due to current rejection from VDDIN to VDDCORE, the current consumption in Deep Mode cannot be guaranteed. Instead, 60 µA is guaranteed whatever the condition. Problem Fix/Workaround None. 40.11.13.2 Voltage Regulator: Load Versus Temperature Maximum load is 50 mA at 85 °C (instead of 100 mA). Maximum load is 100 mA at 70°C. Problem Fix/Workaround None. 40.11.14 Watchdog Timer (WDT) 40.11.14.
40.12 SAM7S128 Errata - Revision A Parts Refer to Section 40.1 “Marking” on page 595. Important: Section 40.12.13.1 ”WDT: The Watchdog Timer May Lock the Device in a Reset State” 40.12.1 Chip ID 40.12.1.1 Wrong Chip ID Value The Chip ID is 0x270C 0740 instead of 0x270A 0740. Problem Fix/Workaround None. 40.12.2 Analog-to-Digital Converter (ADC) 40.12.2.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register).
40.12.2.6 ADC: GOVRE Bit is not Set when Reading CDR When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on channel “x” with the following conditions: • EOC[x] already active, • DRDY already active, • GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.12.2.
40.12.3 Non Volatile Memory Bits (NVM Bits) 40.12.3.1 NVM Bits: Write/Erase Cycles Number The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit. This maximum number of write/erase cycles is not applicable to 128 KB Flash memory, it remains at 10K for the Flash memory. Problem Fix/Workaround None. 40.12.4 Parallel Input/Output Controller (PIO) 40.12.4.
40.12.5 Power Management Controller (PMC) 40.12.5.1 PMC: Slow Clock Selected in PMC and a Transition Occurs on PA1 Under certain rare circumstances, when CSS = 00 in PMC_MCKR, and PA1 is set as an input and a transition occurs on PA1, device malfunction might occur. Problem Fix/Workaround Do not transition PA1 as an input when CSS = 00 in PMC_MCKR. 40.12.5.2 PMC: Programming CSS in PMC_MCKR Register Under certain rare circumstances, reprogramming the CSS value in the PMC_MCKR register (i.
None. 40.12.6.4 PWM: Constraints on Duty Cycle Value Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode may change the polarity of the signal. Problem Fix/Workaround Do not set PWM_CDTYx at 0 in center aligned mode. Do not set PWM_CDTYx at 0 or 1 in left aligned mode. 40.12.6.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register.
Problem Fix/Workaround In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers. 40.12.8.4 SPI: Chip Select and Fixed Mode In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip select 0, the output spi_size sampled by the PDC will depend on the field, BITS (Bits per Transfer) of SPI_CSR0 register, whatever the selected Chip select is.
40.12.9.2 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge (rising or falling) of synchro has a Start Delay equal to zero. Problem Fix/Workaround None. 40.12.9.
40.12.10.3 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset. Problem Fix/Workaround The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before disabling the TWI. 40.12.10.
Constraints on the transmitter device connected to the SAM7S USART receiver side: The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP condition is taken into account by the receiver state machine. After this STOP condition, as there is no valid data, the receiver state machine will go in idle mode and enable the RXBRK flag. 40.12.11.5 USART: DCD is active High instead of Low The DCD signal is active at High level in the USART Modem Mode.
Problem Fix/Workaround Two workarounds are possible. 1. Either do not use the Watchdog Timer with the Watchdog fault Interrupt enabled (WDFIEN set at 1), 2. or set WDD to 0xFFF and in addition use only one of the following values for WDV: 0xFFF, 0xDFF, 0xBFF, 0x9FF, 0x7FF, 0x77F, 0x6FF, 0x67F, 0x5FF, 0x57F, 0x4FF, 0x47F, 0x3FF, 0x37F, 0x2FF, 0x27F, 0x1FF, 0x1BF, 0x17F, 0x13F, 0x0FF, 0x0DF, 0x0BF, 0x09F, 0x07F, 0x06F, 0x05F, 0x04F, 0x03F, 0x037, 0x02f, 0x027, 0x01F, 0x01B, 0x017, 0x013 and 0x00F.
40.13 SAM7S128 Errata - Revision B Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S128 Revision B chip ID is: 0x270A 0741. 40.13.1 Analog-to-Digital Converter (ADC) 40.13.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.13.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.13.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.13.1.
This maximum number of write/erase cycles is not applicable to 128 KB Flash memory, it remains at 10K for the Flash memory. Problem Fix/Workaround None. 40.13.3 Parallel Input/Output Controller (PIO) 40.13.3.1 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31 When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.
Problem Fix/Workaround None. 40.13.4.4 PWM: Constraints on Duty Cycle Value Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode may change the polarity of the signal. Problem Fix/Workaround Do not set PWM_CDTYx at 0 in center aligned mode. Do not set PWM_CDTYx at 0 or 1 in left aligned mode. 40.13.4.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register.
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between transfers. 40.13.6.4 SPI: SPCK Behavior in Master Mode SPCK pin can toggle out before the first transfer in Master Mode. Problem Fix/Workaround In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers. 40.13.6.
40.13.7 Synchronous Serial Controller (SSC) 40.13.7.1 SSC: Periodic Transmission Limitations in Master Mode If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 40.13.7.2 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge (rising or falling) of synchro has a Start Delay equal to zero. Problem Fix/Workaround None. 40.13.
40.13.8.2 TWI: Software Reset When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 40.13.8.3 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
None. 40.13.9.4 USART: RXBRK Flag Error in Asynchronous Mode In receiver mode, when there are two consecutive characters (without timeguard in between), RXBRK is not taken into account. As a result, the RXBRK flag is not enabled correctly and the frame error flag is set. Problem Fix/Workaround Constraints on the transmitter device connected to the SAM7S USART receiver side: The transmitter may use the timeguard feature or send two STOP conditions.
40.14 SAM7S128 Errata - Revision C Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S128 Revision C chip ID is 0x270A 0742. 40.14.1 Embedded Flash Controller (EFC) 40.14.1.1 EFC: Embedded Flash Access Time 1 The embedded Flash maximum access time is 20 MHz (instead of 30 MHz) at zero Wait State (FWS = 0). The maximum operating frequency with one Wait State (FWS = 1) is 48.1 MHz (instead of 55 MHz). Above 48.1 MHz and up to 55 MHz, two Wait States (FWS = 2) are required.
40.14.3.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational. Problem Fix/Workaround Do not write 0 in the period register. 40.14.3.3 PWM: Counter Start Value In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1. Problem Fix/Workaround None. 40.14.4 Real Time Timer (RTT) 40.14.4.
40.15 SAM7S128 Errata - Revision D Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S128 Revision C chip ID is 0x270A0743. 40.15.1 Embedded Flash Controller (EFC) 40.15.1.1 EFC: Embedded Flash Access Time 1 The embedded Flash maximum access time is 20 MHz (instead of 30 MHz) at zero Wait State (FWS = 0). The maximum operating frequency with one Wait State (FWS = 1) is 48.1 MHz (instead of 55 MHz). Above 48.1 MHz and up to 55 MHz, two Wait States (FWS = 2) are required.
40.15.3.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational. Problem Fix/Workaround Do not write 0 in the period register. 40.15.3.3 PWM: Counter Start Value In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1. Problem Fix/Workaround None. 40.15.4 Real Time Timer (RTT) 40.15.4.
40.16 SAM7S64 Errata - Manufacturing Number 58814G Refer to Section 40.1 “Marking” on page 595. 40.16.1 Analog-to-Digital Converter (ADC) 40.16.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.16.1.
• previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.16.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.16.1.
However, this does not prevent JTAG operations. Problem Fix/Workaround The JTAG port remains operational even if the failure on TDI has happened. Therefore the users can develop their applications in normal conditions, except the overall system power consumption might be higher. It is recommended to handle the devices carefully during PCB soldering and to correctly ground the manufacturing equipment.
Set the I/O to VDDIO by internal or external pull-up. 40.16.5.2 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31 When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.45 V This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V and 25 µA at 1.8V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.
Problem Fix/Workaround Do not set PWM_CDTYx at 0 in center aligned mode. Do not set PWM_CDTYx at 0 or 1 in left aligned mode. 40.16.6.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
40.16.8.5 SPI: Chip Select and Fixed Mode In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip select 0, the output spi_size sampled by the PDC will depend on the field, BITS (Bits per Transfer) of SPI_CSR0 register, whatever the selected Chip select is.
• CPOL = 1 and NCPHA = 0 • Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1 • Transmitting with the slowest chip select and then with the fastest one, then an additional on output SPCK during the second transfer.
40.16.10 Two-wire Interface (TWI) 40.16.10.1 TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 40.16.10.2 TWI: Software Reset When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 40.16.10.
40.16.10.5 TWI: Possible Receive Holding Register Corruption When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs. Problem Fix/Workaround The user must be sure that received data is read before transmitting any new data. 40.16.11 Universal Synchronous Asynchronous Receiver Transmitter (USART) 40.16.11.
None. 40.16.12.2 Voltage Regulator: Load Versus Temperature Maximum load is 50 mA at 85 °C (instead of 100 mA). Maximum load is 100 mA at 70°C. Problem Fix/Workaround None.
40.17 SAM7S64 Errata - Revision A Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S64 Revision A chip ID is 0x2709 0540. 40.17.1 Analog-to-Digital Converter (ADC) 40.17.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.17.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.17.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.17.1.
40.17.2 Non Volatile Memory Bits (NVM Bits) 40.17.2.1 NVM Bits: Write/Erase Cycles Number The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit. This maximum number of write/erase cycles is not applicable to 64 KB Flash memory, it remains at10K for the Flash memory. Problem Fix/Workaround None. 40.17.3 Parallel Input/Output Controller (PIO) 40.17.3.
40.17.4 Pulse Width Modulation Controller (PWM) 40.17.4.1 PWM: Update when PWM_CCNTx = 0 or 1 If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is directly modified when writing the Channel Update Register. Problem Fix/Workaround Check the Channel Counter Register before writing the update register. 40.17.4.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround None. 40.17.6.2 SPI: Bad tx_ready behavior when CSAAT=1 and SCBR = 1 If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been transferred in the shifter. This can imply for example, that the second data is sent twice. Problem Fix/Workaround Do not use the combination CSAAT=1 and SCBR =1. 40.17.6.
40.17.6.8 SPI: Disable Issue The SPI Command “SPI Disable” is not possible during a transfer, it must be performed only after TX_EMPTY rising else there is everlasting dummy transfers occur. Problem Fix/Workaround None. 40.17.6.9 SPI: Software Reset and SPIEN Bit The SPI Command “software reset” does not reset the SPIEN config bit. Therefore rewriting an SPI enable command does not set TX_READY, TX_EMPTY flags. Problem Fix/Workaround Send SPI disable command after a software reset. 40.17.6.
40.17.7.3 SSC: Transmitter Limitations in Slave Mode If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during data emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is lost. This problem does not exist when generating a periodic synchro. Problem Fix/Workaround The data need to be delayed for one bit clock period with an external assembly.
40.17.8.4 TWI: NACK Status Bit Lost During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set. Problem Fix/Workaround The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission is not completed. TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR. 40.17.8.
40.17.10 Voltage Regulator 40.17.10.1 Voltage Regulator: Current Consumption in Deep Mode Current consumption in Deep Mode is maximum 60 µA instead of 25 µA. Due to current rejection from VDDIN to VDDCORE, the current consumption in Deep Mode cannot be guaranteed. Instead, 60 µA is guaranteed whatever the condition. Problem Fix/Workaround None. 40.17.10.2 Voltage Regulator: Load Versus Temperature Maximum load is 50 mA at 85 °C (instead of 100 mA). Maximum load is 100 mA at 70°C.
40.18 SAM7S64 Errata - Revision B Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S64 Revision B chip ID is: 0x2709 0543. 40.18.1 Analog-to-Digital Converter (ADC) 40.18.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.18.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.18.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.18.1.
40.18.2 Non Volatile Memory Bits (NVM Bits) 40.18.2.1 NVM Bits: Write/Erase Cycles Number The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit. This maximum number of write/erase cycles is not applicable to 64 KB Flash memory, it remains at10K for the Flash memory. Problem Fix/Workaround None. 40.18.3 Parallel Input/Output Controller (PIO) 40.18.3.
Problem Fix/Workaround Do not write 0 in the period register. 40.18.4.3 PWM: Counter Start Value In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1. Problem Fix/Workaround None. 40.18.4.4 PWM: Constraints on Duty Cycle Value Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode may change the polarity of the signal. Problem Fix/Workaround Do not set PWM_CDTYx at 0 in center aligned mode.
40.18.6.3 SPI: Bad tx_ready behavior when CSAAT=1 and SCBR = 1 If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been transferred in the shifter. This can imply for example, that the second data is sent twice. Problem Fix/Workaround Do not use the combination CSAAT=1 and SCBR =1. 40.18.6.
None. 40.18.6.10 SPI: Software Reset and SPIEN Bit The SPI Command “software reset” does not reset the SPIEN config bit. Therefore rewriting an SPI enable command does not set TX_READY, TX_EMPTY flags. Problem Fix/Workaround Send SPI disable command after a software reset. 40.18.6.
Problem Fix/Workaround The data need to be delayed for one bit clock period with an external assembly. In the following schematic, TD, TK and NRST are SAM7S signals, TXD is the delayed data to connect to the device. 40.18.8 Two-wire Interface (TWI) 40.18.8.1 TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 40.18.8.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR. 40.18.8.5 TWI: Possible Receive Holding Register Corruption When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs. Problem Fix/Workaround The user must be sure that received data is read before transmitting any new data. 40.18.
Problem Fix/Workaround None. 40.18.10.2 Voltage Regulator: Load Versus Temperature Maximum load is 50 mA at 85 °C (instead of 100 mA). Maximum load is 100 mA at 70°C. Problem Fix/Workaround None.
40.19 SAM7S64 Errata - Revision C Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S64 Revision C chip ID is 0x27090544 40.19.1 Parallel Input/Output Controller (PIO) 40.19.1.1 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31 When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.45 V This condition causes a leakage through VDDIO.
None. 40.19.3 Real Time Timer (RTT) 40.19.3.1 RTT: Possible Event Loss when Reading RTT_SR If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event. Problem Fix/Workaround: The software must handle the RTT event as an interrupt and should not poll RTT_SR.
40.20 SAM7S321 Errata - Revision A Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S321 Revision A chip ID is: 0x2708 0342. 40.20.1 Analog-to-Digital Converter (ADC) 40.20.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.20.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.20.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.20.1.
40.20.2 Parallel Input/Output Controller (PIO) 40.20.2.1 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31 When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.45 V This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V and 25 µA at 1.8V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.
Problem Fix/Workaround Do not set PWM_CDTYx at 0 in center aligned mode. Do not set PWM_CDTYx at 0 or 1 in left aligned mode. 40.20.3.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
Problem Fix/Workaround Use the CS in PIO mode when PDC mode is required and CS has to be maintained between transfers. 40.20.5.5 SPI: SPCK Behavior in Master Mode SPCK pin can toggle out before the first transfer in Master Mode. Problem Fix/Workaround In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers. 40.20.5.
40.20.6 Synchronous Serial Controller (SSC) 40.20.6.1 SSC: Periodic Transmission Limitations in Master Mode If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 40.20.6.2 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge (rising or falling) of synchro has a Start Delay equal to zero. Problem Fix/Workaround None. 40.20.
Problem Fix/Workaround None. 40.20.7.3 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset. Problem Fix/Workaround The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before disabling the TWI. 40.20.7.
40.20.8.4 USART: XOFF Character Bad Behavior The XOFF character is sent only when the receive buffer is detected full. While the XOFF is being sent, the remote transmitter is still transmitting. As only one Holding register is available in the receiver, characters will be lost in reception. This makes the software handshaking functionality ineffective. Problem Fix/Workaround None. 40.20.8.5 USART: DCD is active High instead of Low The DCD signal is active at High level in the USART Modem Mode.
40.21 SAM7S32 Errata - Manufacturing Number 58814G Refer to Section 40.1 “Marking” on page 595. 40.21.1 Analog-to-Digital Converter (ADC) 40.21.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.21.1.
• previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.21.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.21.1.
However, this does not prevent JTAG operations. Problem Fix/Workaround The JTAG port remains operational even if the failure on TDI has happened. Therefore the users can develop their applications in normal conditions, except the overall system power consumption might be higher. It is recommended to handle the devices carefully during PCB soldering and to correctly ground the manufacturing equipment.
Problem Fix/Workaround Set the I/O to VDDIO by internal or external pull-up. 40.21.5.2 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31 When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.45 V This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V and 25 µA at 1.8V.
40.21.6.4 PWM: Constraints on Duty Cycle Value Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode may change the polarity of the signal. Problem Fix/Workaround Do not set PWM_CDTYx at 0 in center aligned mode. Do not set PWM_CDTYx at 0 or 1 in left aligned mode. 40.21.6.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register.
selected Chip select is. For example, if SPI_CSR0 is configured for a 10-bit transfer whereas SPI_CSR1 is configured for an 8-bit transfer, when a transfer is performed in Fixed mode through the PDC, on Chip select 1, the transfer will be considered as a HalfWord transfer. Problem Fix/Workaround If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the BITS field of the SPI_CSR0 must be configured in 8 bits, in the same way as the BITS field of the CSRy Register. 40.
• Transmitting with the slowest chip select and then with the fastest one, then an additional on output SPCK during the second transfer. pulse is generated Problem Fix/Workaround Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1. If all chip selects are configured with Baudrate = 1, the issue does not appear. 40.21.8 Synchronous Serial Controller (SSC) 40.21.8.
40.21.9 Two-wire Interface (TWI) 40.21.9.1 TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 40.21.9.2 TWI: Software Reset When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 40.21.9.
CTS must not go low during a time slot occurring between 2 Master Clock periods before the starting bit and 16 Master Clock periods after the rising edge of the starting bit. 40.21.10.3 USART: Hardware Handshaking – Two Characters Sent If CTS switches from 0 to 1 during the TX of a character and if the holding register (US_THR) is not empty, the content of US_THR will also be transmitted. Problem Fix/Workaround Don't use the PDC in transmit mode and do not fill US_THR before TXEMPTY is set at 1. 40.21.10.
40.22 SAM7S32 Errata - Revision A Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S32 Revision A chip ID is 0x2708 0340. 40.22.1 Analog-to-Digital Converter (ADC) 40.22.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.22.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.22.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.22.1.
40.22.2 Non Volatile Memory Bits (NVM Bits) 40.22.2.1 NVM Bits: Write/Erase Cycles Number The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit. This maximum number of write/erase cycles is not applicable to 64 KB Flash memory, it remains at10K for the Flash memory. Problem Fix/Workaround None. 40.22.3 Parallel Input/Output Controller (PIO) 40.22.3.
40.22.4 Pulse Width Modulation Controller (PWM) 40.22.4.1 PWM: Update when PWM_CCNTx = 0 or 1 If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is directly modified when writing the Channel Update Register. Problem Fix/Workaround Check the Channel Counter Register before writing the update register. 40.22.4.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround None. 40.22.6.2 SPI: Bad tx_ready behavior when CSAAT=1 and SCBR = 1 If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been transferred in the shifter. This can imply for example, that the second data is sent twice. Problem Fix/Workaround Do not use the combination CSAAT=1 and SCBR =1. 40.22.6.
40.22.6.8 SPI: Disable Issue The SPI Command “SPI Disable” is not possible during a transfer, it must be performed only after TX_EMPTY rising else there is everlasting dummy transfers occur. Problem Fix/Workaround None. 40.22.6.9 SPI: Software Reset and SPIEN Bit The SPI Command “software reset” does not reset the SPIEN config bit. Therefore rewriting an SPI enable command does not set TX_READY, TX_EMPTY flags. Problem Fix/Workaround Send SPI disable command after a software reset. 40.22.6.
40.22.7.3 SSC: Transmitter Limitations in Slave Mode If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during data emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is lost. This problem does not exist when generating a periodic synchro. Problem Fix/Workaround The data need to be delayed for one bit clock period with an external assembly.
40.22.8.4 TWI: NACK Status Bit Lost During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set. Problem Fix/Workaround The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission is not completed. TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR. 40.22.8.
40.22.10 Voltage Regulator 40.22.10.1 Voltage Regulator: Current Consumption in Deep Mode Current consumption in Deep Mode is maximum 60 µA instead of 25 µA. Due to current rejection from VDDIN to VDDCORE, the current consumption in Deep Mode cannot be guaranteed. Instead, 60 µA is guaranteed whatever the condition. Problem Fix/Workaround None. 40.22.10.2 Voltage Regulator: Load Versus Temperature Maximum load is 50 mA at 85 °C (instead of 100 mA). Maximum load is 100 mA at 70°C.
40.23 SAM7S32 Errata - Revision B Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S32 Revision B chip ID is 0x2708 0341. 40.23.1 Analog-to-Digital Converter (ADC) 40.23.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.23.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.23.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.23.1.
40.23.2 Parallel Input/Output Controller (PIO) 40.23.2.1 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31 When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabilizes at VPull-up. Vpull-up VPull-up Min VPull-up Max VDDIO - 0.65 V VDDIO - 0.45 V This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V and 25 µA at 1.8V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.
Problem Fix/Workaround Do not set PWM_CDTYx at 0 in center aligned mode. Do not set PWM_CDTYx at 0 or 1 in left aligned mode. 40.23.3.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between transfers. 40.23.5.5 SPI: SPCK Behavior in Master Mode SPCK pin can toggle out before the first transfer in Master Mode. Problem Fix/Workaround In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers. 40.23.5.
Assert the Last Transfer Command (NPCS de-activation) for the last character of each slave. 40.23.5.12 SPI: Bad Serial Clock Generation on 2nd Chip Select Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0. This occurs using SPI with the following conditions: • Master Mode • CPOL = 1 and NCPHA = 0 • Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e.
40.23.7 Two-wire Interface (TWI) 40.23.7.1 TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 40.23.7.2 TWI: Software Reset When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None. 40.23.7.
40.23.7.5 TWI: Possible Receive Holding Register Corruption When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs. Problem Fix/Workaround The user must be sure that received data is read before transmitting any new data. 40.23.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) 40.23.8.
40.24 SAM7S161 Errata - Revision A Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S161 Revision A chip ID is 0x2705 0241. 40.24.1 Analog-to-Digital Converter (ADC) 40.24.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.24.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.24.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.24.1.
Problem Fix/Workaround Check the Channel Counter Register before writing the update register. 40.24.2.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational. Problem Fix/Workaround Do not write 0 in the period register. 40.24.2.3 PWM: Counter Start Value In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1. Problem Fix/Workaround None. 40.24.2.
Problem Fix/Workaround Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1. If all chip selects are configured with Baudrate = 1, the issue does not appear. 40.24.5 Synchronous Serial Controller (SSC) 40.24.5.1 SSC: Periodic Transmission Limitations in Master Mode If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
40.24.6 Universal Synchronous Asynchronous Receiver Transmitter (USART) 40.24.6.1 USART: DCD is active High instead of Low The DCD signal is active at High level in the USART Modem Mode. DCD should be active at Low level. Problem Fix/Workaround Add an inverter.
40.25 SAM7S16 Errata - Revision A Parts Refer to Section 40.1 “Marking” on page 595. Note: AT91SAM7S16 Revision A chip ID is 0x2705 0240. 40.25.1 Analog-to-Digital Converter (ADC) 40.25.1.1 ADC: DRDY Bit Cleared The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag. Problem Fix/Workaround: None 40.25.1.
• GOVRE inactive, • previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”. GOVRE should be set but is not. Problem Fix/Workaround None 40.25.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being already active, GOVRE does not rise. Note: OVRE[x] rises as expected. Problem Fix/Workaround None 40.25.1.
Problem Fix/Workaround Check the Channel Counter Register before writing the update register. 40.25.2.2 PWM: Update when PWM_CPRDx = 0 When Channel Period Register equals 0, the period update is not operational. Problem Fix/Workaround Do not write 0 in the period register. 40.25.2.3 PWM: Counter Start Value In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1. Problem Fix/Workaround None. 40.25.2.
Problem Fix/Workaround Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1. If all chip selects are configured with Baudrate = 1, the issue does not appear. 40.25.5 Synchronous Serial Controller (SSC) 40.25.5.1 SSC: Periodic Transmission Limitations in Master Mode If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
40.25.6 Universal Synchronous Asynchronous Receiver Transmitter (USART) 40.25.6.1 USART: DCD is active High instead of Low The DCD signal is active at High level in the USART Modem Mode. DCD should be active at Low level. Problem Fix/Workaround Add an inverter.
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 752
Revision History In the tables that follow, the most recent revision appears first. Version 6175L Change Request Ref Comments Section 39. ”SAM7S Ordering Information” updated product Ordering Code for SAM7S128 and SAM7S256 MLR rev. D. in Table 39-1, “SAM7S Series Ordering Information” 8380/8467 Section 9.5 ”Debug Unit”, “Chip ID Registers” on page 31, added CHIP ID for SAM7S128 Rev D and SAM7S256 Rev D.
Version 6175K Version 6175J Change Request Ref Comments Debug and Test Features: Table 12-2, “SAM7S Series Debug Unit Chip ID” updated. 7044 ERRATA: 2 columns added to Table 40-1, “Errata Summary Table”: SAM7256/128 Rev C and SAM7S64 Rev C. Corresponding sections added. Section 40.5 ”SAM7S512 Errata - Revision B Parts” added. Table 40-1, “Errata Summary Table” updated too. 7185 Ordering Information: MRL C column added to Table 39-1, “SAM7S Series Ordering Information”.
Change Request Ref Version 6175I Comments Overview: Section ”Features”, “Debug Unit (DBGU)” updated with “Mode for General Purpose 2-wire UART Serial Communication” Section 7.4 ”Peripheral DMA Controller”, added list of PDC priorities. Section 9. ”System Controller”, Figure 9-1 and Figure 9-2 RTT is reset by “power_on_reset”. Section 9.1.1 ”Brownout Detector and Power-on Reset”, fourth paragraph reduced. Section 12.5.5 ”ID Code Register”, added “The JTAG ID is used in the IEEE 1149.1 JTAG Boundary Scan.
Change Request Ref Version 6175I Comments (Continued) “SAM7S512 Errata - Revision A Parts” added, Section 40.4.6.1 ”SPI: Software Reset Must be Written Twice” “SAM7S256 Errata - Revision B Parts” added, Section 40.8.6.1 ”SPI: Software Reset Must be Written Twice” “SAM7S128 Errata - Revision B Parts” added, Section 40.13.6.1 ”SPI: Software Reset Must be Written Twice” “SAM7S321 Errata - Revision A Parts” added, Section 40.20.5.
Version 6175H Change Request Ref. Comments Overview: “Features” on page 1 (and all of datasheet) Added AT91SAM7S16/161 to product family. See: Table 1-1, “Configuration Summary,” on page 3 Section 8.6 “SAM7S161/16” on page 19. rfo Section 9.5 ”Debug Unit” Chip ID updated. 4325 Section 6. ”I/O Lines Considerations”, JTAG Port Pin, Test Pin, Erase Pin, updated. 5063 ADC: Section 36.6.2 ”ADC Mode Register”, STARTUP and PRESCAL bitfields updated (width expanded). AIC: Section 23.8.
Version 6175H Change Request Ref. Comments (Continued) UDP: Table 35-2, “USB Communication Flow”, Supported Endpoint column updated In the USB_CSR register, the control endpoints are not effected by the fit field, “EPEDS: Endpoint Enable Disable” on page 533, Updated: write1 =....in “RX_DATA_BK0: Receive Data Bank 0” bit field of USB_CSR register. Updated: write1 =....in “TXPKTRDY: Transmit Packet Ready” bit field of USB_CSR register. Section 35.6.
Version 6175H Change Request Ref. Comments (Continued) All AT91SAM7S: “Analog-to-Digital Converter (ADC)” , errata applies to all AT91SAM7S products. “USART: DCD is active High instead of Low” , errata applies to all AT91SAM7S products. “SPI: Bad Serial Clock Generation on 2nd Chip Select” , errata applies to all AT91SAM7S products. “SPI: Bad Behavior when CSAAT = 1 and SCBR = 1”, errata applies to all AT91SAM7S products. Version 6175G 4752 rfo AT91SAM7S256 Mfg # 58818C, AT91SAM7S256 Parts.
Version 6175F Change Request Ref. Comments “Features” on page 1 (global) QFN packages changed to 64- and 48-pad QFN Manchester Encoder/Decoder removed from USART. “Features” on page 1, Table 1-1, “Configuration Summary,” on page 3, Section 4. ”Package and Pinout”Section 39. ”SAM7S Ordering Information”and global, AT91SAM7S512 added to product family. Section 4.1 ”64-lead LQFP and 64-pad QFN Package Outlines” and Section 4.3 ”48-lead LQFP and 48pad QFN Package Outlines”added (replace Mechanical Overview).
Version 6175F Change Request Ref. Comments (Continued) TC, Table 32-1, “Timer Counter Clock Assignment,” on page 389 has been added. Section 32.5.4 ”External Event/Trigger Conditions” TIOB defined as external event signal..... updated ”EEVT: External Event Selection” page 412, TIOB chosen as external event signal..... updated in footnote TWI, ”Two-wire Interface (TWI) User Interface” page 294, UNRE and OVRE bit fields removed from TWI Status and Interrupt register tables.
Version 6175F Change Request Ref. Comments (Continued) Section 37. ”SAM7S Electrical Characteristics” AT91SAM7S512 specific info added and changes to the following tables.
Version 6175E Change Request Ref Comments “Features” on page 1, Table 1-1, “Configuration Summary,” on page 3, Section 4. ”Package and Pinout”“Absolute Maximum Ratings” on page 557, Table 37-1, “Thermal Resistance Data,” on page 537and Section 39. ”SAM7S Ordering Information”QFN package information added. Section 40. ”Errata” QFN package errata added, Section 40. ”Errata” SPI: SPCK Behavior in Master Mode added. Section 40. ”Errata” PIO: Leakage in worst case changed to 9 µA.
Version 6175C Version 6175B Change Request Ref Comments AT91SAM7S321 addresses redefined:Table 22-4, “User Area Addresses,” on page 171 Values given in PIO Line column: Table 22-5, “Pins Driven during Boot Program Execution,” on page 171 #1217 Section 40. ”Errata” added lines and note to the following: Section 40.6.3.1 ”MCK: Limited Master Clock Frequency Ranges” AT91SAM7S256 Section 40.11.3.1 ”MCK: Limited Master Clock Frequency Ranges” AT91SAM7S128 Section 40.16.3.
Version 6175A Comments Change Request Ref First issue SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 765
SAM7S Series [DATASHEET] 6175M–ATARM–26-Oct-12 766
Table of Contents Features ..................................................................................................... 1 1 Description ................................................................................................ 3 1.1Configuration Summary of the SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321, SAM7S32, SAM7S161 and SAM7S16 3 2 Block Diagram .......................................................................................... 4 3 Signal Description ....................
8.5SAM7S321/32 .........................................................................................................19 8.6SAM7S161/16 .........................................................................................................19 8.7Memory Mapping .....................................................................................................21 8.8Embedded Flash .....................................................................................................22 8.
12.2Block Diagram .......................................................................................................47 12.3Application Examples ............................................................................................48 12.4Debug and Test Pin Description ............................................................................50 12.5Functional Description ...........................................................................................51 13 Reset Controller (RSTC) .....
19.2Functional Description .........................................................................................105 19.3Embedded Flash Controller (EFC) User Interface ...............................................114 20 Fast Flash Programming Interface (FFPI) .......................................... 123 20.1Overview ..............................................................................................................123 20.2Parallel Fast Flash Programming ....................................
25.3Processor Clock Controller ..................................................................................191 25.4USB Clock Controller ...........................................................................................192 25.5Peripheral Clock Controller ..................................................................................192 25.6Programmable Clock Output Controller ...............................................................192 25.7Programming Sequence ........................
29.7Two-wire Interface (TWI) User Interface .............................................................309 30 Two Wire Interface (TWI) SAM7S161/16 ............................................. 319 30.1Overview ..............................................................................................................319 30.2List of Abbreviations ............................................................................................319 30.3Block Diagram .............................................
33.6Timer Counter (TC) User Interface ......................................................................463 34 Pulse Width Modulation Controller (PWM) ........................................ 481 34.1overview ..............................................................................................................481 34.2Block Diagram .....................................................................................................481 34.3I/O Lines Description ...................................
38.2LQFP Packages ..................................................................................................585 38.3QFN Packages ....................................................................................................588 38.4Soldering Profile ..................................................................................................592 39 SAM7S Ordering Information .............................................................. 593 40 Errata .......................................
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