Datasheet

60
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
13.3.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports
the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is per-
formed when the processor reset is released.
13.3.4.1 Power-up Reset
When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates
at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the
device.
The startup time, as shown in Figure 13-4, is hardcoded to comply with the Slow Clock Oscillator startup time. After
the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset.
When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately.
Figure 13-4. Power-up Reset
SLCK
periph_nreset
proc_nreset
Main Supply
POR output
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
Startup Time
MCK
Processor Startup
= 3 cycles
Any
Freq.