Datasheet

596
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
40.2 Errata Summary by Product and Revision or Manufacturing Number
Table 40-1. Errata Summary Table
SAM7Sx Product
Revision or Manufacturing Number
Errata
SAM7S512 rev A SAM7S512 rev B SAM7S256/128 58818C SAM7S256/128 rev A SAM7S256/128 rev B SAM7S256/128 rev C SAM7S256/128 rev D SAM7S64/32 58814G SAM7S64 rev A SAM7S64 rev B SAM7S64 rev C SAM7S32 rev A SAM7S32 rev B SAM7S321 rev A SAM7S161 rev A SAM7S16 rev A
Part
Chip ID Wrong Chip ID Value
XX
ADC DRDY Bit Cleared
XXXXX XXX X X X
ADC DRDY not Cleared on Disable
XXXXX XXX X X X
ADC DRDY Possibly Skipped due to CDR Read
XXXXX XXX X X X
ADC Possible Skip on DRDY when Disabling a Channel
XXXXX XXX X X X
ADC GOVRE Bit is not Updated
XXXXX XXX X X X
ADC GOVRE Bit is not Set when Reading CDR
XXXXX XXX X X X
ADC GOVRE Bit is not Set when Disabling a Channel
XXXXX XXX X X X
ADC OVRE Flag Behavior
XXXXX XXX X X X
ADC EOC Set although Channel Disabled
XXXXX XXX X X X
ADC Spurious Clear of EOC Flag
XXXXX XXX X X X
ADC Sleep Mode
XXXXX XXX X X X
EFC
Embedded Flash Access Time 1
XXX
Embedded Flash Access Time 2
X
JTAG Recommendation for TDI Pin
X
MCK Limited Master Clock Frequency Ranges
XX
NVM Bits Write/Erase Cycles Number
XXX XXX X
PIO Leakage on PA17 - PA20
XXXX XX X
PIO
Electrical Characteristics on NRST and PA0-PA16 and
PA21-31
XXXXXXXXXXXX X
PIO Drive Low NRST, PA0-PA16 and PA21-PA31
XXXXXXXXXXXX X
PMC
Slow Clock Selected in PMC and a Transition Occurs on
PA1
XX
PMC Programming CSS in PMC_MCKR Register
XX
PWM Update when PWM_CCNTx = 0 or 1
XXXXXXXXXXXX X X
PWM Update when PWM_CPRDx = 0
XXXXXXXXXXXX X X
PWM Counter Start Value
XXXXXXXXXXXX X X
PWM Constraints on Duty Cycle Value
XXXXX XXX X X X
PWM Behavior of CHIDx Status Bits in the PWM_SR Register
XXXXX XXX X X X
RTT Possible Event Loss when Reading RTT_SR
XXXXXXXXXX X X
RTT RTT_VR May be Corrupted
XX
SPI Software Reset Must be Written Twice
XX X X X
SPI Pulse Generation on SPCK
XXX X X
SPI Bad Behavior when CSAAT = 1 and SCBR = 1
XXXXX XXX X X