Datasheet

Table Of Contents
489
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
34.5.3.4 Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the correspond-
ing channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is dis-
abled by setting the corresponding bit in the PWM_IDR register.
34.6 Pulse Width Modulation Controller (PWM) User Interface
Note: 1. Some registers are indexed with “ch_num” index ranging from 0 to X-1.
Table 34-2. Register Mapping
Offset
(1)
Register Name Access Reset
0x00 PWM Mode Register PWM_MR Read/Write 0
0x04 PWM Enable Register PWM_ENA Write-only -
0x08 PWM Disable Register PWM_DIS Write-only -
0x0C PWM Status Register PWM_SR Read-only 0
0x10 PWM Interrupt Enable Register PWM_IER Write-only -
0x14 PWM Interrupt Disable Register PWM_IDR Write-only -
0x18 PWM Interrupt Mask Register PWM_IMR Read-only 0
0x1C PWM Interrupt Status Register PWM_ISR Read-only 0
0x4C - 0xFC Reserved
0x100 - 0x1FC Reserved
0x200 + ch_num * 0x20 + 0x00 PWM Channel Mode Register PWM_CMR Read/Write 0x0
0x200 + ch_num * 0x20 + 0x04 PWM Channel Duty Cycle Register PWM_CDTY Read/Write 0x0
0x200 + ch_num * 0x20 + 0x08 PWM Channel Period Register PWM_CPRD Read/Write 0x0
0x200 + ch_num * 0x20 + 0x0C PWM Channel Counter Register PWM_CCNT Read-only 0x0
0x200 + ch_num * 0x20 + 0x10 PWM Channel Update Register PWM_CUPD Write-only -