Datasheet

570
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
37.5 PLL Characteristics
Note: Startup time depends on PLL RC filter. A calculation tool is provided by Atmel.
37.6 Master Clock Characteristics
37.7 I/O Characteristics
Criteria used to define the maximum frequency of the I/Os:
• output duty cycle (30%-70%)
• minimum output swing: 100mV to VDDIO - 100mV
• Addition of rising and falling time inferior to 75% of the period
Table 37-13. Phase Lock Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
F
OUT
Output Frequency:
SAM7S64/32/312/161/16
Field out of CKGR_PLL is:
00 80 160 MHz
10 150 200 MHz
F
OUT
Output Frequency:
SAM7S512/256/128
Field out of CKGR_PLL is:
00 80 160 MHz
10 150 180 MHz
F
IN
Input Frequency 1 32 MHz
I
PLL
Current Consumption
Active mode 4 mA
Standby mode 1 µA
Table 37-14. Master Clock Waveform Parameters
Symbol Parameter Conditions Min Max Units
1/(t
CPMCK
) Master Clock Frequency 55 MHz
Table 37-15. I/O Characteristics
Symbol Parameter Conditions Min Max Units
FreqMax
I01
Pin Group 1
(1)
frequency
3.3V domain
(4)
12.5 MHz
1.8V domain
(5)
4.5 MHz
PulseminH
I01
Pin Group 1
(1)
High Level Pulse Width
3.3V domain
(4)
40 ns
1.8V domain
(5)
110 ns
PulseminL
I01
Pin Group 1
(1)
Low Level Pulse Width
3.3V domain
(4)
40 ns
1.8V domain
(5)
110 ns
FreqMax
I02
Pin Group 2
(2)
frequency
3.3V domain
(4)
25 MHz
1.8V domain
(5)
14 MHz
PulseminH
I02
Pin Group 2
(2)
High Level Pulse Width
3.3V domain
(4)
20 ns
1.8V domain
(5)
36 ns