Datasheet

539
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
36. Analog-to-Digital Converter (ADC)
36.1 Overview
The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also
integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital conversions of 8 analog lines. The
conversions extend from 0V to ADVREF.
The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for
all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the
ADTRG pin or internal triggers from Timer Counter output(s) are configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These fea-
tures reduce both power consumption and processor intervention.
Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time.
36.2 Block Diagram
Figure 36-1. Analog-to-Digital Converter Block Diagram
ADC Interrupt
ADTRG
VDDIN
ADVREF
GND
Trigger
Selection
Control
Logic
Successive
Approximation
Register
Analog-to-Digital
Converter
Timer
Counter
Channels
User
Interface
AIC
Peripheral Bridge
APB
PDC
ASB
Dedicated
Analog
Inputs
Analog Inputs
Multiplexed
with I/O lines
AD-
AD-
AD-
PIO
AD-
AD-
AD-
ADC Controller
PMC
MCK
ADC cell