Datasheet

91
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
18. Memory Controller (MC)
18.1 Overview
The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the
ARM7TDMI processor and the Peripheral DMA Controller. It features a bus arbiter, an address decoder, an abort status, a
misalignment detector and an Embedded Flash Controller.
18.2 Block Diagram
Figure 18-1. Memory Controller Block Diagram
ARM7TDMI
Processor
Bus
Arbiter
Peripheral
DMA
Controller
Memory Controller
Abort
ASB
Abort
Status
Address
Decoder
User
Interface
Peripheral 0
Peripheral 1
Internal
RAM
APB
APB
Bridge
Misalignment
Detector
From Master
to Slave
Peripheral N
Embedded
Flash
Controller
Internal
Flash
EMAC
DMA