Datasheet
635
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
42. Revision History
Version Comments
Change
Request
Ref.
6120A 10-Oct-05 First issue
6120B 17-Oct-05
Updated product functionalities in ”Features” on page 1, Figure 2-1 on page 4, Section 9.5 ”Debug Unit”
on page 29, and Figure 11-1 on page 27
05-456
Corrected PLL output range maximum value in Section 9.2 ”Clock Generator” on page 27, Figure 18-3 in
Section 18.3.2.1 ”Internal Memory Mapping” on page 93 and Table 38-12, “Phase Lock Loop
Characteristics,” on page 602.
05-491
Updated information in Power Supplies on page 9
Updated field Part Number in Section 12.5.5 ”ID Code Register” on page 55.
Updated Chip ID in Section 9.5 ”Debug Unit” on page 29 and in Section 12.5.3 ”Debug Unit” on page 48. 05-472
Removed references to PGMEN2 in Section 20. ”Fast Flash Programming Interface (FFPI)” on page 117. 05-464
Updated “ARCH: Architecture Identifier” in Debug Unit with new values for AT91SAM7XCxx series and
AT91SAM7Xxx series.
05-459
Updated CAN bit timing configuration in Section 36.6.4.1 ”CAN Bit Timing Configuration” on page 502
and in Section 36.8.6 ”CAN Baudrate Register” on page 533.
05-419
Added Section 38.8.4 ”EMAC Characteristics” on page 609. 05-469
Updated AT91SAM7X Ordering information. 05-470
6120C 26-Oct-05
Replaced Section 29. ”Two-wire Interface (TWI)” on page 279. 05-516
6120D 03-Feb-06
Section 41. ”AT91SAM7X512/256/128 Errata”
Device package/product number changed
Section 41.2.1 ”Ethernet MAC (EMAC)” RMII mode is not functional
The sections listed below have been added to the Errata:
Section 41.2.3 ”Pulse Width Modulation Controller (PWM)”
Section 41.2.5 ”Serial Peripheral Interface (SPI)”
Section 41.2.6 ”Synchronous Serial Controller (SSC)”
Section 41.2.7 ”Two-wire Interface (TWI)”
Section 41.2.8 ”Universal Synchronous Asynchronous Receiver Transmitter (USART)”
#1767
6120E 04-Apr-06
The following errata have been added:
Section 41.2.1.2 ”EMAC: Possible Event Loss when Reading EMAC_ISR”
Section 41.2.1.3 ”EMAC: Possible Event Loss when Reading the Statistics Register Block”
Section 41.2.5.3 ”SPI: SPCK Behavior in Master Mode”
Section 41.2.2.1 ”PIO: Leakage on PB27 - PB30”: worst case leakage changed to 9 µA
#2455
#2605