Datasheet

632
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
41.3.7 Two-wire Interface (TWI)
41.3.7.1 TWI: Clock Divider
The value of CLDIV x 2
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
CKDIV
must be less than or equal to 8191⋅
Problem Fix/Workaround
None.
41.3.7.2 TWI: Disabling Does not Operate Correctly
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with
the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register
(TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts
must be disabled before disabling the TWI.
41.3.7.3 TWI: NACK Status Bit Lost
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection
and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as
long as transmission is not completed.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of
the TWI_SR.
41.3.7.4 TWI: Possible Receive Holding Register Corruption
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the
TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor
OVERRUN status bits are set if this occurs.
Problem Fix/Workaround
The user must be sure that received data is read before transmitting any new data.
41.3.7.5 TWI: Software Reset
when a software reset is performed during a frame and when TWCK is low, it is impossible to ini-
tiate a new transfer in READ or WRITE mode.
Problem Fix/Workaround
None.